in 21 Days
Laura Lemay Charles L. Perkins
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About This Book
This book teaches you all about the Java
Carleton University Department of Systems and Computer Engineering SYSC 2004 Fall 2009 Lab 8 - Inheritance Objective The objective of this lab is to gain more experience with inheritance and abstract classes. Getting Started 1. Download file chess.zip fro
Due Oct. 20/2015 (beginning of class)
1. Write complete verilog code (i.e complete module) for the following state diagram. Inputs for the
module should be x, y, clk and reset, output is z and states are S1,S5,S6,S7,S9,S10. Reset sta
Due Nov. 26/2015 (in class)
1. (a) Draw a state diagram and state table and show what if anything is wrong with the following
synchronous state machine that has asynchronous input X and state variables A & B?
(b) If possible, draw a
The demo1 file was compiled and simulated. The data for this can be seen in
table 1. It was seen that the simulation ended at 120ns. This is what was expected because the
finish statement was initialized to be completed after 120 time units. The i
Due Oct. 6, 2016 (beginning of class)
1. (a) Implement an 4 to 1 mux using only CMOS inverters, NOR and NAND gates
(b) Implement a 4 to 1 multiplexer using only CMOS transmission gates and inverters.
(c) Which approach is better and
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Lab 3: Sequential CMOS
When the CLK is high the output switches to VD which is 2 volts. When the clock is
low, it switches to VQ which is 0.5 volts. The waveforms are shown in Figure 1 below
and a zoomed in version of the data is
Some people may do it this way. This is not the way it was suppose to be done.
7 7 7
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A Teaching Assistant attempted this method. Do you like this method? What if the system was 4th order or higher?