Santa Clara University Dept. of Electrical Engineering ELEN 21 (Logic Design) Spring 2002 HOMEWORK #8 SOLUTIONS (240pts. total) Sequential Circuit Design (30 pts. each) 1. Text 4.16 2. Text 4.17
3. Text 4.21
4. Text 4.23
5. Text 4.30
Registers (30 pts. ea

ELEN21/COEN21:
Digital Design
Lecture #19:
Prof. Bob Schaffer
MWF: 9:15am-10:20am
1
Logistics
Homework:
HW4 Graded: Mean: 47.5; Median: 48.8; Range: 19.5-59 (out of 60)
HW5: grader is working on it
HW6 due Thursday at 11:59pm
Quizzes:
Quiz 5 Results:

ELEN21/COEN21:
Digital Design
Lecture #17:
Prof. Bob Schaffer
MWF: 9:15am-10:20am
1
Logistics
Homework:
HW4 not graded yet.
HW5 due last night at 11:59pm (late days allowed through Sat. PM)
HW6 will be assigned tonight (posted by Sat. AM)
Quizzes:
Q

ELEN21/COEN21:
Digital Design
Lecture #16:
Prof. Bob Schaffer
MWF: 9:15am-10:20am
1
Logistics
Homework:
HW3 graded: Mean: 87.0; Median: 88.0; Range: 65-100 (one 0 not included in the averages)
HW4 not graded yet.
HW5 due tomorrow at 11:59pm
Quizzes:

ELEN21/COEN21:
Digital Design
Lecture #12:
Prof. Bob Schaffer
MWF: 9:15am-10:20am
1
Logistics
Homework:
HW3 due last night only 1 late day allowed meaning, no later than tonight at 11:59pm!
HW4 a short HW will be assigned on 10/17 AFTER the first midte

ELEN21/COEN21:
Digital Design
Lecture #22:
Prof. Bob Schaffer
MWF: 9:15am-10:20am
1
Logistics
Homework:
HW5 Results: Mean: 81.0; Median: 83.0; Range: 35-99 (out of 100)
HW6: Grader shooting for end of the week
HW7: due Friday, 11/11 1 late day allowed

ELEN21/COEN21:
Digital Design
Lecture #18:
Prof. Bob Schaffer
MWF: 9:15am-10:20am
1
Quiz 5
2
Quiz 5 Solutions
1) (4 points) Given one 4-to-1 MUX and access to the input variables (A,B,C) and their
complements and no other logic gates - implement , , = (,

ELEN21/COEN21:
Digital Design
Lecture #13:
Prof. Bob Schaffer
MWF: 9:15am-10:20am
1
Logistics
Homework:
HW4 due Friday at 11:59pm (only one late day allowed no later than Saturday)
HW5 will be assigned on Friday PM and due next Thursday (back to the re

ELEN21/COEN21:
Digital Design
Lecture #15:
Prof. Bob Schaffer
MWF: 9:15am-10:20am
1
Quiz 4
2
Quiz 4 Solutions
1) (4 points) Based on the design for the adders designed in HW4 (shown below), label all
inputs, outputs, and intermediate wires of the four-bi

Handout 12
ELEN21/COEN21: Fall 16
10/21/2016
ELEN21/COEN21: HW #4 (60 points) SOLUTIONS
Submissions should be a PDF made via Camino. I do not expect typed or nicely formatted HW. Scans of
handwritten assignments are completely acceptable (and, frankly, ex

Handout 15
ELEN21/COEN21: Fall 16
10/28/2016
ELEN21/COEN21: HW #5 (100 points) SOLUTIONS
Submissions should be a PDF made via Camino. I do not expect typed or nicely formatted HW. Scans of
handwritten assignments are completely acceptable (and, frankly, e

Handout 19
ELEN21/COEN21: Fall 16
11/4/2016
ELEN21/COEN21: HW #7 (100 points) DUE THU NOV 11, 2016 at 11:59PM
Submissions should be a PDF made via Camino. I do not expect typed or nicely formatted HW. Scans of
handwritten assignments are completely accept

Handout 9
ELEN21/COEN21: Fall 16
10/14/2016
ELEN21/COEN21: HW #3 (100 points) SOLUTIONS
Submissions should be a PDF made via Camino. I do not expect typed or nicely formatted HW. Scans of
handwritten assignments are completely acceptable (and, frankly, ex

Handout 18
ELEN21/COEN21: Fall 16
11/4/2016
ELEN21/COEN21: HW #6 (100 points) SOLUTIONS
Submissions should be a PDF made via Camino. I do not expect typed or nicely formatted HW. Scans of
handwritten assignments are completely acceptable (and, frankly, ex

ELEN21/COEN21:
Digital Design
Lecture #4:
Prof. Bob Schaffer
MWF: 9:15am-10:20am
1
Logistics
Questionnaire: All but one
Registrations complete got a full 36 in the class
Homework: HW1 due Wed. via PDF through Camino
Quizzes:
Quiz 1 today
Quiz 2 next

ELEN21/COEN21:
Digital Design
Lecture #6:
Prof. Bob Schaffer
MWF: 9:15am-10:20am
1
Logistics
Office hours: no Friday office hours either next week will be normal
Homework:
HW1 solutions emailed last night (to all that submitted HW1)
HW2 posted this af

Working with delays:
The No Delay (ND) line is the output if there were no delay at all.
Transport Delay (TD) output takes the ND output and duplicates it one propagation delay unit later.
Finally, for Inertial Delay (ID) the output needs to be investi

ELEN21/COEN21:
Digital Design
Lecture #21:
Prof. Bob Schaffer
MWF: 9:15am-10:20am
1
Quiz #6
2
Quiz #6 Solutions
1) (3 points) How many manufacturer connections (in the HW these were represented as Xs
with circles around them) would be present in a 32x4 R

ELEN21/COEN21:
Digital Design
Lecture #11:
Prof. Bob Schaffer
MWF: 9:15am-10:20am
1
Logistics
Homework:
HW2- Mean: 94.8; Median: 97; Range: 65-100
HW3 due Thursday, 10/13 at 11:59pm (only 1 late day allowed)
HW4 a short HW will be assigned on 10/17 AFT

ELEN21/COEN21:
Digital Design
Lecture #20:
Prof. Bob Schaffer
MWF: 9:15am-10:20am
1
Logistics
Homework:
HW5: grader is working on it
HW6: late days allowed through Saturday PM; Solutions should be available Friday evening
HW7: posted by Saturday AM -

Santa Clara University Dept. of Electrical Engineering ELEN 21 (Logic Design) Spring 2002 HOMEWORK #4 SOLUTIONS Analysis of Combinational Circuit (20 pts. each) 1. Text 3-1 2. Text 3-2
Page 1 of 8
3. Text 3-4
Page 2 of 8
Design of Combinational Circuit (3

Santa Clara University Dept. of Electrical Engineering ELEN 21 (Logic Design) Spring 2002 HOMEWORK #6 SOLUTIONS Full adders (30 pts. each) 1. Text 3.27 To implement a binary full-adder with a dual 4-to-1-line multiplexer and a single inverter. Consider th

Santa Clara University Dept. of Electrical Engineering ELEN 21 (Logic Design) Spring 2002 HOMEWORK #2 SOLUTIONS CORRECTED April 22, 2002 (See corrections below in RED for Problem 4(Text 2.19 and Problem 7(Text 2.23(b) SOP and POS 1. Text 2.12 (20 pts.) a)

Santa Clara University Dept. of Electrical Engineering ELEN 21 (Logic Design) Spring 2002
HOMEWORK #9 SOLUTIONS (210pts. total)
Applications of registers (30pts. each) 1. FD4CE is a 4-bit data registers with clock enable (CE) and asynchronous clear (CLR).

Santa Clara University Dept. of Electrical Engineering ELEN 21 (Logic Design) Spring 2002 HOMEWORK #3 SOLUTIONS More simplification 1. Text 2.20 (20pts.) (a) Prime = WXY', WYZ, XZ, W'XY, W'Y'Z Essential = WXY', WYZ, W'XY, W'Y'Z F = WXY' + WYZ + W'XY + W'Y

Binary, other base numbers
To convert to base n:
1. Divide number by n, yielding output O and reminder R. This is the least significant digit.
2. Divide O by n, which yields output O_1 and remainder R_1. This is the second least significant bit.
3. Repeat