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The first step in using a Karnaugh map to minimize a Boolean expression is to
map the expression onto the grid. A Boolean expression is mapped in the same way
as a truth table is constructed. Where a one would be found in the output of th
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change in any one input will change the output. A satisfied AND or OR gate has a
true output, whereas a satisfied NAND or NOR gate has a false output. We
sometimes identify the input logic variables A, B, C, etc. with an nbit number
ABC.
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Semiconductor electronic devices
49
Slope
is E
E
ptype
ntype
V
Electron
energy
0
Majority
carriers
Depletion
region
Majority
carriers
Good
Poor
conductor conductor
Good
conductor
Figure 3.6 The pn junction diode
the junction and the ptype material acqu
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IC
RC
IB
+
RB
+
VCE
+VBE
+
VB
RE
VCC
IE
Figure 3.27 Equivalent a.c. circuit to Figure 3.25.
RB
B
+
+
VB
IB
C
hie
hfeIB
RC
E
RE
iE
Figure 3.28 Equivalent a.c. circuit smallsignal model to Figure 3.25.
which gives
IB
VB
RB hie 1 hfe RE
3:2
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As an illustration, let us use both methods to convert the fraction 0.5937610
into its binary equivalent. We will use two methods: power series and
multiplication methods.
Power series method
First, we will take a power series of 8, with
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(a)
(b)
Figure 3.48 MOSFET OR structure: (a) ntype; (b) ptype.
3.6.5.5 MOSFET logic gate analysis
We now use the enhancement MOSFET circuit shown in Figure 3.49 to carry
out the switching analysis (referring to the characteristics in Fig
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VDD
Q3
Vout
V1
Q1
Q2
V2
Figure 3.59 Circuit for Q3.6.
VDD
Q3
V1
V2
Q1
Vout
Q2
Figure 3.60 Circuit for Q3.7.
Q3.5 Show that the circuit in Figure 3.58 functions as a NAND gate if the
output is taken at Vo2. Construct a truth table.
Q3.6 Sho
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I
A
R2
R1
R3
R5
R4
+
V1
+
V2
Figure 2.21 Circuit for Q2.4.
Q2.5 In Figure 2.22, F1 and F2 are fuses. Under normal conditions they are
modeled as short circuits. However, if excess current flows through a fuse,
it melts and consequently blo
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CHAPTER 4
Digital electronics
Chapter objectives
When you have finished this chapter you should be able to:
&
handle combinational logic design using a truth table;
&
understand Karnaugh maps and logic design;
&
understand combinational logic modules such
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3.6.6.1 The CMOS inverter
The most important CMOS gate is the CMOS inverter. It consists of only two
transistors, an nchannel device and a pchannel device (Figure 3.51).
The nchannel transistor provides the switch connection to ground w
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The MOSFET, is similar to the JFET but exhibits an even larger resistive input
impedance due to the thin layer of silicon dioxide that is used to insulate the gate
from the semiconductor channel (hence the MOSFETs alternative name: the
ins
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Vdd
M1
V1
M2
V2
Vout
M3
V1
M4
V2
Figure 3.53 CMOS equivalent NOR gate.
Case 1: V1 0 V; V2 0 V: In this case, M1 and M2 are on, but M3 and M4
are off . Thus, Vout VD 5 V. This condition is shown in Figure 3.54(a).
Case 2: V1 5 V; V2 0 V: In
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VDD
D
ID
RD
+
VDS
S
RS
G
+
VG
RG

Figure 3.31 Biasing an nchannel JFET.
ID
IDSS
Vgs = 0V
2V
4V
6V
VDS
Figure 3.32 nchannel JFET drain characteristic.
Figure 3.31 shows the biasing of an nchannel JFET. A very importa
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4.2.4 Base conversion
4.2.4.1 Conversion from binary, octal, or hex to decimal
Notice that in our examples, each group of bits on the right corresponds to a digit
in the higher based number on the left. It is also easy to convert the othe
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+
IB
B
IC
n
VCE
C
VEB
VCB
59
+
E
p
n
E
C
B
VCB
VBE
VCE > VBE
IC > IB
Figure 3.18 (a) npn BJT biased for operation; and (b) voltage levels developed within the biased
semiconductor.
knee
IC
constant
IC
IB
IB3
IB2
IB1
nonli
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Digital electronics
111
4.3.3.6 The buffer gate
Buffers return a delayed output which is the same as the input. The schematic
symbol is shown in Figure 4.6, and the truth table is shown in Table 4.8.
4.3.3.7 The tristate buffer (TSB) gate
Tristate buffe
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Digital electronics
D0
D1
D
D2
Q
D
C
Q
D
C
Q
C
Load
Figure 4.54 A data register using the clocked inputs to Dtype flipflops.
Load
D0
D1
D
S
Q
C R Q
D2
D
S
Q
C R Q
D
S
Q
C R Q
Clear
Figure 4.55 A more complicated data register.
4.9.1.2 Shift register
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tD
Delay
D
tD
Figure 4.41 Edge triggering.
Table 4.22 Truth table indicating edge triggering
Q
J
K
C
S
R
Q
0
0
1
1
X
X
0
1
0
1
X
X
#
#
#
#
X
X
1
1
1
1
0
1
1
1
1
1
1
0
no change
0
1
1
0
toggle
1
0
0
1
J
J
J
Q
Q
Q
Q
Q
K
K
(a)
Q
C
C
C
K
S
(b
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Electrical components and circuits
43
Thevenin and Norton equivalent circuits
Q2.6 In Figure 2.23, VS 12 V; R1 7 k; R2 3 k; R3 8 k; R4 6 k.
Determine:
(a) the Thevenin equivalent of the circuit to the left of ab;
(b) the voltage across ab.
Q2.7 In the cir
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Determine:
(a) the Thevenin equivalent of the circuit to the left of YY 0 ;
(b) the voltage between YY 0 .
Solution
(a) Specify the polarity of the Thevenin equivalent voltage:
Using the voltage divider expression:
VTH
VB RL
11 7:2
10:03
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VDD
R1
iD
RD
+
iG
VDS
+ V
GS
R2
RS
Figure 3.37 Selfbiasing circuit for Example 3.3.
Solution
The voltage supply, VDD, appears across the potential divider comprising R1
and R2. Consequently, the base terminal of the transistor will see th
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RG
IB
RB
+
VG
Figure 2.11 A circuit used to illustrate the superposition principle.
By KCL:
IB
VRI
VRI VRI VRI
0
RB
RG
R
IB
1
RB
1
RG
1
R
10
1
1:25
1
1
0:5
0:25
1:47 V
2:23A
2:23B
Suppress the current source by replacing it with an op
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From the universal equation,
iD kvGS VT 2 ;
gm
IDSS
VT 2
2
k
@ kVGS VT
@ID
jIG , VDS
@VGS
@VGS
2kVGS VT :
3:42
3:43
From Equation 3.42:
r
ID
ID
and VGS VT
VGS VT
,
k
k
r
p
p 2 IDSS ID
ID
:
gm 2k
2 kID
k
VT
2
3:43A
3:44
The MOSFET t
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3.6 Active components
The circuits we have encountered so far have been passive and dissipate power.
Even a transformer that is capable of giving a voltage gain to a circuit is not an
active element. Active elements in
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iD
D
+
RD
VDS
G
+
VGG
79
VGS
VDD
S
Figure 3.39 nchannel depletiontype MOSFET biasing.
iD
IDSS
VGS = 0 V
2V
4V
6V
VDS
Figure 3.40 nchannel depletiontype MOSFET drain characteristic.
bias voltage, VGS, can cause no curre
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From the graph shown in Figure 3.45, when Vin is low (0 V), the transistor is in
the cutoff region and little current flows; and consequently,
Vout VCC iC RC VCC,
3:47B
since the second term is almost zero.
Hence, Vout