CSE 260 Introduction to Digital Logic and Computer Design
Jonathan Turner
Exam 1 Solutions
2/13/2014
1. (10 points) Draw a logic diagram that implements the expression A(B+C)(C+D)(B+D)
directly (do no
CSE 260 Digital Computers: Organization and Logical Design
Midterm Exam
Jon Turner
3/2/06
1. (8 points) What is the dual of the expression AB + (C + D)(A + B) + (A+B )C?
What is its complement?
Using
CSE 260 Digital Computers: Organization and Logical Design
Midterm Exam
Jon Turner
3/1/2007
1. (10 points) List the minterms and maxterms for the expression AB + (A + B)C + (A+C )B?
Express the comple
CSE 260 Digital Computers: Organization and Logical Design
Quiz 1
Jon Turner
9/7/2010
1. (6 points) State briefly what each of the following instructions for the Washu2 processor
does.
Immediate Load
CSE 260 Digital Computers: Organization and Logical Design
Quiz 1
Jon Turner
1/26/06
1. (4 points) What is the binary representation of the decimal value 216?
If you interpret the binary value from th
CS/EE 260 Digital Computers: Organization and Logical Design
Quiz 1
Jon Turner
1/25/2007
1. (4 points) What is the 2s complement of the binary value 0101 0100? Write this as a hex value as well.
Draw
CSE 260 Digital Computers: Organization and Logical Design
Quiz 2
Jon Turner
9/21/2010
1. (6 points) Draw a diagram of an 8:1 multiplexor using two 4:1 multiplexors and a 2:1
multiplexor as building b
CSE 260 Digital Computers: Organization and Logical Design
Quiz 2
Jon Turner
2/2/2006
1. (5 points) Complete the timing diagram shown below for the given circuit.
-1-
2. (5 points) The simulation outp
CSE 260 Digital Computers: Organization and Logical Design
Quiz 2
Jon Turner
2/5/2008
1. (5 points) Does the following VHDL specification implement a combinational circuit? Justify
your answer.
entity
CS/EE 260 Digital Computers: Organization and Logical Design
Quiz 2
Jon Turner
2/1/2007
1. (5 points) Simplify the following expression (AB+C)D+B(C+D) using Boolean algebra. Make it as simple as you c
CSE 260 Digital Computers: Organization and Logical Design
Midterm Solutions
Jon Turner
2/28/2008
1. (10 points). The figure below shows a simulation of the washu-1 processor, with some items
blanked
CSE 260 Digital Computers: Organization and Logical Design
Quiz 3
Jon Turner
10/12/2010
1. (5 points) Given the following signal declarations.
signal x: std_logic_vector(19 downto 0);
signal y: std_lo
CSE 260 Digital Computers: Organization and Logical Design
Midterm Exam Solutions
Jon Turner
3/1/2007
1. (10 points) List the minterms and maxterms for the expression AB + (A + B)C + (A+C )B?
ABC 000
CSE 260 Digital Computers: Organization and Logical Design
Midterm Exam Solutions
Jon Turner
3/2/06
1. (8 points) What is the dual of the expression AB + (C + D)(A + B) + (A+B )C? (A+B)(CD+AB)(AB )+C)
CSE 260 Digital Computers: Organization and Logical Design
Final Exam
Jon Turner
5/3/2007
1. (10 points) Draw a transistor-level diagram (using n-FETs and p-FETs) of a CMOS NOR gate with 3 inputs, A,
CSE 260 Digital Computers: Organization and Logical Design
Exam 2
Jon Turner
11/4/2010
1. (10 points). The table at right shows a table with 5 rows and three columns with each
column having a heading.
CSE 260 Digital Computers: Organization and Logical Design
Exam 2 Solutions
Jon Turner
1. (10 points). The table at right shows a table with 5 rows and three columns with each
column having a heading.
CSE 260 Digital Computers: Organization and Logical Design
Exam 1
Jon Turner
9/30/2010
1. (10 points). The diagram below shows the processor registers for the Washu-2 processor and
the contents of sev
CSE 260 Digital Computers: Organization and Logical Design
Exam 1 Solutions
Jon Turner
1.
(10 points). The diagram below shows the processor registers for the Washu-2 processor
and the contents of sev
CSE 260 Digital Computers: Organization and Logical Design
Final Exam Solutions
Jon Turner
5/9/06
1. (12 points) The expression (A + D) (B + C )(C + D ) has the minterm ABCD and the maxterm (A+B+C+D).
CSE 260 Digital Computers: Organization and Logical Design
Final Exam Solutions
Jon Turner
5/1/2008
1. (8 points) Consider the two timing diagrams shown below. One shows the output of a CMOS NAND gate
CSE 260 Digital Computers: Organization and Logical Design
Final Exam Solutions
Jon Turner
5/3/2007
1. (10 points) Draw a transistor-level diagram (using n-FETs and p-FETs) of a NOR gate with 3 inputs
CSE 260 Digital Computers: Organization and Logical Design
Final Exam Solutions
Jon Turner
1. (10 points). Define combinational circuit.
A combinational circuit is one in which the circuits outputs de
CSE 260 Digital Computers: Organization and Logical Design
Final Exam
Jon Turner
5/9/06
1. (12 points) The expression (A + D) (B + C )(C + D ) has the minterm ABCD and the maxterm (A+B+C+D). List thre
CSE 260 Digital Computers: Organization and Logical Design
Final Exam
Jon Turner
5/1/2008
1. (8 points) Consider the two timing diagrams shown below. One shows the output of a CMOS NAND gate in respon
CSE 260 Digital Computers: Organization and Logical Design
Quiz 3
Jon Turner
2/16/2006
1. (6 points) (6 points) Fill in the Karnaugh map below so that it corresponds to the function F(A,B,C,D) = m(2,3
CSE 260 Digital Computers: Organization and Logical Design
Quiz 2
Jon Turner
2/5/2008
1. (5 points) Consider a sequential circuit with two inputs A, B a single output X and two state
flip flops. The n
CSE 260 Digital Computers: Organization and Logical Design
Midterm
Jon Turner
2/28/2008
1. (10 points). The figure below shows a simulation of the washu-1 processor, with some items
blanked out. Fill
CSE 260 Digital Computers: Organization and Logical Design
Jon Turner
Exam 2
Your name:
3/27/2014
1. (15 points). The VHDL shown below is taken from an implementation of the stackCalc
module from Lab
CSE 260 Digital Computers: Organization and Logical Design
Exam 2
Jon Turner
3/28/2012
1. (15 points). Draw a diagram for a circuit that implements the VHDL module shown below.
Your diagram may includ