CSE 260 Introduction to Digital Logic and Computer Design
Jonathan Turner
Exam 1 Solutions
2/13/2014
1. (10 points) Draw a logic diagram that implements the expression A(B+C)(C+D)(B+D)
directly (do not simplify first), using only simple gates.
B
C
D
A
Sim
CSE 260 Digital Computers: Organization and Logical Design
Midterm Exam
Jon Turner
3/2/06
1. (8 points) What is the dual of the expression AB + (C + D)(A + B) + (A+B )C?
What is its complement?
Using Boolean algebra, derive an expression equivalent to AB
CSE 260 Digital Computers: Organization and Logical Design
Midterm Exam
Jon Turner
3/1/2007
1. (10 points) List the minterms and maxterms for the expression AB + (A + B)C + (A+C )B?
Express the complement of AB + (A + B)C + (A+C )B in the simplest form yo
CSE 260 Digital Computers: Organization and Logical Design
Quiz 1
Jon Turner
9/7/2010
1. (6 points) State briefly what each of the following instructions for the Washu2 processor
does.
Immediate Load - 1xxx
Direct Store - 5xxx
Branch if Positive - 03xx
-1
CSE 260 Digital Computers: Organization and Logical Design
Quiz 1
Jon Turner
1/26/06
1. (4 points) What is the binary representation of the decimal value 216?
If you interpret the binary value from the first part as an eight bit signed value in 2scompleme
CS/EE 260 Digital Computers: Organization and Logical Design
Quiz 1
Jon Turner
1/25/2007
1. (4 points) What is the 2s complement of the binary value 0101 0100? Write this as a hex value as well.
Draw a circuit using simple gates only (e.g. and, or, invert
CSE 260 Digital Computers: Organization and Logical Design
Quiz 2
Jon Turner
9/21/2010
1. (6 points) Draw a diagram of an 8:1 multiplexor using two 4:1 multiplexors and a 2:1
multiplexor as building blocks. Label the data inputs D0, D1,.,D7 and the contro
CSE 260 Digital Computers: Organization and Logical Design
Quiz 2
Jon Turner
2/2/2006
1. (5 points) Complete the timing diagram shown below for the given circuit.
-1-
2. (5 points) The simulation output below shows selected signals from the processor intr
CSE 260 Digital Computers: Organization and Logical Design
Quiz 2
Jon Turner
2/5/2008
1. (5 points) Does the following VHDL specification implement a combinational circuit? Justify
your answer.
entity foo is port (
a,b,c,d: in std_logic_vector(7 downto 0;
CS/EE 260 Digital Computers: Organization and Logical Design
Quiz 2
Jon Turner
2/1/2007
1. (5 points) Simplify the following expression (AB+C)D+B(C+D) using Boolean algebra. Make it as simple as you can.
-1-
2. (5 points) The figure below shows a portion
CSE 260 Digital Computers: Organization and Logical Design
Midterm Solutions
Jon Turner
2/28/2008
1. (10 points). The figure below shows a simulation of the washu-1 processor, with some items
blanked out. Fill in the blanks below with the correct value fr
CSE 260 Digital Computers: Organization and Logical Design
Quiz 3
Jon Turner
10/12/2010
1. (5 points) Given the following signal declarations.
signal x: std_logic_vector(19 downto 0);
signal y: std_logic_vector(3 to 10);
What is the value of xright?
What
CSE 260 Digital Computers: Organization and Logical Design
Midterm Exam Solutions
Jon Turner
3/2/06
1. (8 points) What is the dual of the expression AB + (C + D)(A + B) + (A+B )C? (A+B)(CD+AB)(AB )+C)
What is its complement? (A+B)(CD+AB)(AB )+C) = (A+B)(C
CSE 260 Digital Computers: Organization and Logical Design
Midterm Exam Solutions
Jon Turner
3/1/2007
1. (10 points) List the minterms and maxterms for the expression AB + (A + B)C + (A+C )B?
ABC 000 001 010 011 100 101 110 111
F 0 1 1 1 0 1 0 1
minterms
CSE 260 Digital Computers: Organization and Logical Design
Exam 2
Jon Turner
11/4/2010
1. (10 points). The table at right shows a table with 5 rows and three columns with each
column having a heading. Write a VHDL definition of a record type that would be
CSE 260 Digital Computers: Organization and Logical Design
Exam 2 Solutions
Jon Turner
1. (10 points). The table at right shows a table with 5 rows and three columns with each
column having a heading. Write a VHDL definition of a record type that would be
CSE 260 Digital Computers: Organization and Logical Design
Exam 1
Jon Turner
9/30/2010
1. (10 points). The diagram below shows the processor registers for the Washu-2 processor and
the contents of several memory locations. In the space to the right of the
CSE 260 Digital Computers: Organization and Logical Design
Exam 1 Solutions
Jon Turner
1.
(10 points). The diagram below shows the processor registers for the Washu-2 processor
and the contents of several memory locations. In the space to the right of the
CSE 260 Digital Computers: Organization and Logical Design
Final Exam Solutions
Jon Turner
5/9/06
1. (12 points) The expression (A + D) (B + C )(C + D ) has the minterm ABCD and the maxterm (A+B+C+D). List three more of its minterms and three more of its
CSE 260 Digital Computers: Organization and Logical Design
Final Exam Solutions
Jon Turner
5/1/2008
1. (8 points) Consider the two timing diagrams shown below. One shows the output of a CMOS NAND gate in response to a change on one of its inputs. The othe
CSE 260 Digital Computers: Organization and Logical Design
Final Exam Solutions
Jon Turner
5/3/2007
1. (10 points) Draw a transistor-level diagram (using n-FETs and p-FETs) of a NOR gate with 3 inputs, A, B and C.
A B C (A+B+C)'
Suppose all three inputs a
CSE 260 Digital Computers: Organization and Logical Design
Final Exam Solutions
Jon Turner
1. (10 points). Define combinational circuit.
A combinational circuit is one in which the circuits outputs depend only on the current value of the
inputs.
Is the ci
CSE 260 Digital Computers: Organization and Logical Design
Final Exam
Jon Turner
5/9/06
1. (12 points) The expression (A + D) (B + C )(C + D ) has the minterm ABCD and the maxterm (A+B+C+D). List three more of its minterms and three more of its maxterms.
CSE 260 Digital Computers: Organization and Logical Design
Final Exam
Jon Turner
5/1/2008
1. (8 points) Consider the two timing diagrams shown below. One shows the output of a CMOS NAND gate in response to a change on one of its inputs. The other shows th
CSE 260 Digital Computers: Organization and Logical Design
Final Exam
Jon Turner
5/3/2007
1. (10 points) Draw a transistor-level diagram (using n-FETs and p-FETs) of a CMOS NOR gate with 3 inputs, A, B and C.
Suppose all three inputs are low initially and
CSE 260 Digital Computers: Organization and Logical Design
Quiz 3
Jon Turner
2/16/2006
1. (6 points) (6 points) Fill in the Karnaugh map below so that it corresponds to the function F(A,B,C,D) = m(2,3,5,6,12,13), d(A,B,C,D) = m(4,8,9,11,15). Derive a mini
CSE 260 Digital Computers: Organization and Logical Design
Quiz 2
Jon Turner
2/5/2008
1. (5 points) Consider a sequential circuit with two inputs A, B a single output X and two state
flip flops. The next-state and output equations for the circuit are
D1 =
CSE 260 Digital Computers: Organization and Logical Design
Midterm
Jon Turner
2/28/2008
1. (10 points). The figure below shows a simulation of the washu-1 processor, with some items
blanked out. Fill in the blanks below with the correct value from the cor
CSE 260 Digital Computers: Organization and Logical Design
Jon Turner
Exam 2
Your name:
3/27/2014
1. (15 points). The VHDL shown below is taken from an implementation of the stackCalc
module from Lab 3. It shows a slightly simplified version of the code t
CSE 260 Digital Computers: Organization and Logical Design
Exam 2
Jon Turner
3/28/2012
1. (15 points). Draw a diagram for a circuit that implements the VHDL module shown below.
Your diagram may include gates, muxes and one or more 8 bit subtractors (that