CS 573 Algorithms
Sariel Har-Peled
May 29, 2013
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High Performance Computing
Systems
Presenting
Experimental Results
Profiling
Homework
Doug Shook
#1
Presenting Experimental Results
Plots
are great but they must be used correctly
This plot is bad. Why?
2
Presenting Experimental Results
This plot fixes so
High Performance Computing
Systems
Shared Memory
Doug Shook
Shared Memory
Bottlenecks
Trips to memory
Cache coherence
2
Why Multicore?
Shared memory systems used to be purely the
domain of HPC.
What happened?
3
Architecture Types
Four primary architectu
High Performance Computing
Systems
OpenMP
Doug Shook
Project Proposals
Due to me by July 7
One or two paragraphs, by email
Projects:
Paper
Programming
Presentation
2
Automatic Parallelization
Attempts to parallelize serial code
Problems:
Dependence a
High Performance Computing
Systems
Benchmarks
Doug Shook via Roger Chamberlain
What is High Performance?
Based on performance, of course
Many possible interpretations of performance.
What can we use as indicators of performance?
How do we go about measuri
CSE517a Homework 2
M. Neumann
30 Jan 2017
Please keep your written answers brief and to the point. Incorrect or rambling statements
can hurt your score on a question.
If your hand writing is not readable, we cannot give you credit. We recommend you type
RECAP QUIZ INTRO TO ML
T/F: Spam filtering is an example for a regression
problem.
T/F: We can always assume that labels are noise
free.
T/F: Using a (carefully engineered) set of rules for
spam filtering would not work very well.
T/F: Having a
CSE517a Homework 1
M. Neumann
18 Jan 2017
Please keep your written answers brief and to the point. Incorrect or rambling statements
can hurt your score on a question.
If your hand writing is not readable, we cannot give you credit. We recommend you type
CSE 581T: Approximation Algorithms
Homework 1-A
Release: 1-24-2017
Due: in class, Tuesday, 1-31-2017
Make your solutions concise and formal. Your goal is to convince me that you know the solutions.
You are highly encouraged to typeset your solutions in La
CS/EE 260 Digital Computers: Organization and Logical Design
Quiz 1
Jon Turner
1/27/04
1. (5 points) Add the six bit unsigned binary numbers 011001 and 101110. What is the six bit
sum?
Does this six bit addition result in an arithmetic error?
Suppose the
CS/EE 260 Digital Computers: Organization and Logical Design
Final Exam
Jon Turner
5/12/04
1. (16 points) Find the simplest sum-of-products equivalent to the expression below using
Boolean algebra only.
(ABD + BCD + BC D + AC )
Show how your simplified ve
CS/EE 260 Digital Computers: Organization and Logical Design
Final Exam Solutions
Jon Turner
5/12/04
1. (16 points) Find the simplest sum-of-products equivalent to the expression below using
Boolean algebra only.
(ABD + BCD + BC D + AC )
= (A+B+D)(B+C +D)
CS/EE 260 Digital Computers: Organization and Logical Design
Midterm Solutions
Jon Turner
3/4/04
1. (8 points) Draw a logic diagram that directly implements the expression
A(B + CD) + (C + (A+B)D)
(do not simplify the expression first).
How many transisto
CSE 260 Digital Computers: Organization and Logical Design
Final Exam Solutions
Jon Turner
5/11/05
1. (8 points) The expression AD + (B + C )(C + D ) has the minterm ABCD and the maxterm
(A+B+C+D). List four more of its minterms and four more of its maxte
CS/EE 260 Digital Computers: Organization and Logical Design
Quiz 9
Jon Turner
4/4/02
1. (10 points) The state transition diagram shown below is for a simpler version of the arbiter circuit discussed in problem set 9. In this version, there is a fixed pri
CS/EE 260 Digital Computers: Organization and Logical Design
Quiz 10
Jon Turner
4/11/02
1. The simulation output below shows the control signals from the basic processor during the execution of five instructions. Each instruction is "boxed" for clarity. F
CS/EE 260 Digital Computers: Organization and Logical Design
Quiz 6
Jon Turner
3/27/03
1. (10 points) Is the sequential circuit defined by the VHDL code shown below a Mealy model circuit or a Moore model circuit (circle one or the other)? Draw a state dia
CS/EE 260 Digital Computers: Organization and Logical Design
Quiz 7
Jon Turner 4/10/03
1. In this problem, you are to complete the VHDL module below, so that it implements a sequential circuit with two states, up and down. If the circuit is in the up stat
CS/EE 260 Digital Computers: Organization and Logical Design
Quiz 8
Jon Turner 4/17/03
1. The simulation output below is from the basic processor running a program. The boxes outline selected instructions. Identify each of these instructions that are bein
CS/EE 260 Digital Computers: Organization and Logical Design
Quiz 8
Jon Turner
3/28/02
1. (10 points) Draw a state diagram corresponding to the VHDL module shown below. Is this VHDL for a Mealy model circuit or a Moore model circuit? What is the minimum n
CS/EE 260 Digital Computers: Organization and Logical Design
Quiz 7
Jon Turner
3/21/02
1. (6 points) Give the state transition table corresponding to the state diagram shown below. Is this state diagram for a Mealy model circuit or a Moore model circuit?
CS/EE 260 Digital Computers: Organization and Logical Design
Quiz 6
Jon Turner
2/21/02
1. The figure below shows a 4 bit lookahead comparator. If each of the complex gates were replaced by simple gates, what would be the worst-case delay through this circ
CS/EE 260 Digital Computers: Organization and Logical Design
Quiz 5
Jon Turner
2/14/02
1. (6 points) Show how to implement the expression (A + C)D + B D using an 8:1 multiplexor plus one inverter.
2. (4 points) How many simple gates are needed to implemen
CS/EE 260 Digital Computers: Organization and Logical Design
Quiz 5
Jon Turner
3/20/03
1. (10 points) The table shown below is the state transition table for a sequential circuit with two states, one input A and one output X. Give the next state and outpu
CS/EE 260 Digital Computers: Organization and Logical Design
Quiz 4
Jon Turner
2/20/03
1. (10 points) What output value is produced by the circuit defined by the VHDL specification shown below, when the input value is 1100? What unsigned numerical values
CS/EE 260 Digital Computers: Organization and Logical Design
Quiz 4
Jon Turner
2/7/02
1. (6 points) Give a minimal product-of-sums expression for AC + A BD + BC.
2. (4 points) How many transistors are needed to implement the circuit shown below in CMOS te
CS/EE 260 Digital Computers: Organization and Logical Design
Quiz 3
Jon Turner
2/13/03
1. (6 points) List the minterms in the expression A B D + B(CD + A C). If you wish, you may list them numerically.
How many gates of each type are required to implement
CS/EE 260 Digital Computers: Organization and Logical Design
Quiz 3
Jon Turner 1/31/02
1. (5 points) Find the complement of the expression BC + (A + C)B D and write it in minimal sum-of-products form.
2. (5 points) Simplify the logic function F(A,B,C) = m
CS/EE 260 Digital Computers: Organization and Logical Design
Quiz 2
Jon Turner
1/24/02
1. (10 points) How many simple gates of each type are needed to implement the expression shown below (without simplification)? (A + BC)(B + CD) + A(CD + BCD)
Use Boolea