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School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 9 Jon Turner 4/4/02 1. (10 points) The state transition diagram shown below is for a simpler version of the arbiter circuit discussed in problem set 9. In this version, there is a fixed pri
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab OO Patterns Introduction to ACE CS 342: Object-Oriented Software Development Lab What is ACE? OO middleware framework that implements many core design patterns for concurrent communication software Targeted for develope
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab Tools and Techniques Tools and Techniques CS 342: Object-Oriented Software Development Lab Motivation Problem Areas Approaches Tools Suggestions Introduction to Tools and Techniques David L. Levine Christopher D. Gill D
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab OO Programming with C+ Design Principles and Guidelines Overview CS 342: Object-Oriented Software Development Lab Design Principles Important design concepts Useful design principles Evaluation criteria Development Meth
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab Tools and Techniques Dynamic Diagnostic Tools (on Unix) CS 342: Object-Oriented Software Development Lab Process control Process activity Shared resources Dynamic Diagnostic Tools David L. Levine Christopher D. Gill Dep
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab Tools and Techniques Build Control CS 342: Object-Oriented Software Development Lab Why use build control? MAKE Build Control with MAKE David L. Levine Christopher D. Gill Department of Computer Science Washington Unive
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab OO Programming with C+ Background CS 342: Object-Oriented Software Development Lab Single and Multiple Inheritance in C+ David L. Levine Christopher D. Gill Department of Computer Science Washington University, St. Loui
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
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School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
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School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
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School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
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School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
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School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
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School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 9 Jon Turner 4/4/02 1. (10 points) The state transition diagram shown below is for a simpler version of the arbiter circuit discussed in problem set 9. In this version, there is a fixed pri
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
JEE2600 Homework Assignment #8 Problems due Monday, November 15th. Show your work on all problems. 1. Using the following state diagram, create a sequential circuit that will 000 /0 001 /0 X 011 /0 111 /0 QC QBQA 110 /1 X' implement this state diagram and
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
JEE2600 Homework Assignment #10 Solutions 1. Rework test 1 problems (Each problem is worth half of what it was worth on the test). Test answers are posted on the syllabus page. 2. Draw a circuit that implements the following RTL statement using 1-bit regi
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
JEE2600 Homework Assignment #7 Solutions Problems due Monday, November 8th. Show your work on all problems. 1. Problem 7.12 (6 pts) Excitation and output equations: D1 = Q1 + Q2 D2 = Q2X Z = Q1 + Q2 Excitation/transition table; state/output table: 2. Prob
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
JEE2600 Homework Assignment #9 Solutions 1. Assuming ideal timing (propagation delays and setup/hold times are zero) complete the following timing diagram for the 74x194 shift register. Read p.730 for a clarification on the functionality of this chip. (10
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
JEE2600 Homework Assignment #5 Problems due Monday, October 18th. Show your work on all problems. 1. Design an 8:3 encoder that acts like a priority encoder for the lower four inputs, but for the four higher priority inputs both the input and the 7's comp
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
JEE2600 Homework Assignment #4 Solutions 1. Starting at t = 0, draw two timing diagrams for the following schematic when IN changes from 0 to 1 and 1 to 0 using the following propogation delays: A 15ns 12ns tpLH tpHL B 10ns 10ns C 9ns 9ns Draw the timing
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Lab 4 Jon Turner Due 4/1/2013 Review and follow the general instructions from lab 1. In this lab, youll be designing and implementing a circuit that implements the classic 15-puzzle game (see pict
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Lab 5 Jon Turner Due 5/1/2014 Review and follow the general instructions from lab 1. This lab consists of several parts. In the first part, you will be add the following three instructions to the
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Jon Turner Lab 1 Solution 1/28/2014 Part A (20 points). Paste the VHDL for your modified calculator below. Highlight your modifications to the code by making them bold. Note that the next paragrap
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Lab 3 Jon Turner Due 3/4/2014 Review and follow the general instructions from lab 1. In this lab, youll be designing and implementing a stack-based calculator. There will be two parts to this circ
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Lab 2 Jon Turner Due 2/18/2014 Review and follow the general instructions from lab 1. In this lab, you will be designing and implementing a patternMatcher circut. This circuit will detect strings
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Lab 1 Jon Turner Due 1/28/2014 General notes for labs. The labs are intended to give you the opportunity to apply what youve learned in the course to larger problems and to gain some experience wi
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 9 Jon Turner 4/4/02 1. (10 points) The state transition diagram shown below is for a simpler version of the arbiter circuit discussed in problem set 9. In this version, there is a fixed pri
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 10 Jon Turner 4/11/02 1. The simulation output below shows the control signals from the basic processor during the execution of five instructions. Each instruction is "boxed" for clarity. F
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 6 Jon Turner 3/27/03 1. (10 points) Is the sequential circuit defined by the VHDL code shown below a Mealy model circuit or a Moore model circuit (circle one or the other)? Draw a state dia
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 7 Jon Turner 4/10/03 1. In this problem, you are to complete the VHDL module below, so that it implements a sequential circuit with two states, up and down. If the circuit is in the up stat
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 8 Jon Turner 4/17/03 1. The simulation output below is from the basic processor running a program. The boxes outline selected instructions. Identify each of these instructions that are bein
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 8 Jon Turner 3/28/02 1. (10 points) Draw a state diagram corresponding to the VHDL module shown below. Is this VHDL for a Mealy model circuit or a Moore model circuit? What is the minimum n
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 7 Jon Turner 3/21/02 1. (6 points) Give the state transition table corresponding to the state diagram shown below. Is this state diagram for a Mealy model circuit or a Moore model circuit?
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 6 Jon Turner 2/21/02 1. The figure below shows a 4 bit lookahead comparator. If each of the complex gates were replaced by simple gates, what would be the worst-case delay through this circ
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 5 Jon Turner 2/14/02 1. (6 points) Show how to implement the expression (A + C)D + B D using an 8:1 multiplexor plus one inverter. 2. (4 points) How many simple gates are needed to implemen
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 5 Jon Turner 3/20/03 1. (10 points) The table shown below is the state transition table for a sequential circuit with two states, one input A and one output X. Give the next state and outpu
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 4 Jon Turner 2/20/03 1. (10 points) What output value is produced by the circuit defined by the VHDL specification shown below, when the input value is 1100? What unsigned numerical values
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 4 Jon Turner 2/7/02 1. (6 points) Give a minimal product-of-sums expression for AC + A BD + BC. 2. (4 points) How many transistors are needed to implement the circuit shown below in CMOS te
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 3 Jon Turner 2/13/03 1. (6 points) List the minterms in the expression A B D + B(CD + A C). If you wish, you may list them numerically. How many gates of each type are required to implement
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 3 Jon Turner 1/31/02 1. (5 points) Find the complement of the expression BC + (A + C)B D and write it in minimal sum-of-products form. 2. (5 points) Simplify the logic function F(A,B,C) = m
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 2 Jon Turner 1/24/02 1. (10 points) How many simple gates of each type are needed to implement the expression shown below (without simplification)? (A + BC)(B + CD) + A(CD + BCD) Use Boolea
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 1 Jon Turner 1/24/03 1. (4 points) What is the hexadecimal representation of the decimal value 189? Express -42 as an eight bit twos-complement value. -1- 2. (6 points) If our basic process
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 2 Jon Turner 1/30/03 1. (5 points) Draw a circuit that directly implements the logic function (A + C)B + D(AB + C). Do not simplify the expression first. -1- 2. (5 points) Give expressions
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Mid-Term Exam Jon Turner 3/13/03 1. (6 points) List all the minterms for the expression (B + A)C + AC + BC. List the maxterms for the expression. -1- 2. (5 points) Show that the following Boolea
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 1 Jon Turner 1/17/02 1. (4 points) What is the pattern of bits used to represent the integer 937 in BCD? 2. (6 points) If our basic processor begins execution with the first instruction sho
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Mid-Term Exam Jon Turner 2/28/02 1. (5 points) Compute the difference: 011011 001101 using six bit binary arithmetic, by taking the 2s complement of the second operand and then adding. 2. (10 po
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Mid-Term Exam Solutions Jon Turner 2/28/02 1. (5 points) Compute the difference: 011011001101 using six bit binary arithmetic, by taking the 2s complement of the second operand and then adding.
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Mid-Term Exam Solutions Jon Turner 3/13/03 1. (6 points) List all the minterms for the expression (B + A)C + AC + BC. Expanding the expression gives BC + AC + AC + BC = ABC + ABC + ABC + ABC + A
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Final Exam Jon Turner 4/30/02 1. (5 points) Simplify the following expression using the basic identities of Boolean algebra. (A + B)C + AB)BD -1- 2. (14 points) Find a minimum sum of products ex
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Final Exam Jon Turner 5/6/03 1. (10 points) How many simple gates of each type (and, or, inverter) are needed to directly implement the expression A(B+CD)+(A+CD). Find the simplest equivalent su
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Final Exam May 4, 2001 You may have one sheet of notes. No calculators. Write in the spaces provided. Be neat. 1. (4 points) Assuming 8 bit words, what is the binary representation of 79? What is the hexadecimal representation of 79? What is the
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Final Exam Solutions May 4, 2001 You may have one sheet of notes. No calculators. Write in the spaces provided. Be neat. 1. (4 points) Assuming 8 bit words, what is the binary representation of 79? 0100 1111 What is the hexadecimal representatio
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Final Exam Spring 2000 You may use one page of notes. No calculators. Write in the spaces provided. Be neat. 1. (10 points) Write the machine language instructions needed to implement each of the lines of pseudo-code shown below. The list of mac
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Final Exam Solutions Jon Turner 5/6/03 1. (10 points) How many simple gates of each type (and, or, inverter) are needed to directly implement the expression A(B+CD)+(A+CD). 3 ANDs, 3 ORs and 2 i
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 - Exam 2 4/23/2001 1. (10 points) Draw a state diagram for the sequential circuit shown below. W D Q A >C Q D E Clk Q Y Z B >C Q -1- 2. (10 points) Answer the following questions, in connection with the circuit in problem 1. Assume that the flip
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Final Exam Solutions Jon Turner 4/30/02 1. (5 points) Simplify the following expression using the basic identities of Boolean algebra. (A + B)C + AB)BD = (AC + BC + AB)BD = ABCD + ABD = ABD(C +
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 - Exam 1 Solutions 3/5/2001 1. (6 points) Using 40 bits, how many different integers can be represented in (a) binary 2 40 (b) BCD 10 10 (c) 8-bit ASCII? 10 5 2. (12 points) The simulation output on the next page is from an execution of the simp
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 - Exam 2 Solutions 4/23/2001 1. (10 points) Draw a state diagram for the sequential circuit shown below. W D Q A >C Q D E Clk Q Y Z B >C Q AB 00 01 10 11 00 00 01 01 10 10 11 11 EW D ADB 0x 00 0x 00 0x 00 0x 00 10 01 11 11 10 11 11 01 10 00 11 1
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 - Exam 1 3/5/2001 1. (6 points) Using 40 bits, how many different integers can be represented in (a) binary, (b) BCD, (c) 8-bit ASCII? -1- 2. (12 points) The simulation output on the next page is from an execution of the simple processor introdu
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Final Exam Solutions Spring 2000 You may use one page of notes. No calculators. Write in the spaces provided. Be neat. 1. (10 points) Write the machine language instructions needed to implement each of the lines of pseudo-code shown below. The l
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Exam 2 April 13, 2000 You may have one sheet of notes. No calculators. Write in the spaces provided. Be neat. 1. (10 points) Several flip flops and latches are shown below. Identify each one completely (e.g. Master-Slave SR flip flop) and label
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Exam 2 Solutions April 13, 2000 You may have one sheet of notes. No calculators. Write in the spaces provided. Be neat. 1. (10 points) Several flip flops and latches are shown below. Identify each one completely (e.g. Master-Slave SR flip flop)
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Exam 1 Spring 2000 No books, no notes, no calculators. Write in the spaces provided. Be neat. 1. (5 points) What is the binary representation of 678? What is the octal representation? Hexadecimal? 678 = 512 + 166 166 = 128 + 38 38 = 32 + 6 6= 4+
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Exam 1 Spring 2000 No books, no notes, no calculators. Write in the spaces provided. Be neat. 1. (5 points) What is the binary representation of 678? What is the octal representation? Hexadecimal? 2. (5 points) Use a Karnaugh map to find the sim
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Quiz 7 Jon Turner 4/26/05 1. (4 points) Consider a processor with a 2-way set associative cache with a total of 32 words (16 per bank), used for data only. Suppose that a program being executed ha
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Quiz 6 Jon Turner 4/14/05 1. (5 points) Is the sequential circuit shown below, subject to internal hold time violations? If so, show how would you correct them (be specific). Assume that the flip
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 7 Jon Turner 4/27/04 1. (4 points) In the program for the basic processor shown below, the loop is executed 10 times. How many times are instructions retrieved from memory during the execut
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 6 Jon Turner 4/20/04 1. (4 points) The diagram below shows a memory array containing 16 words of 4 bits each. The values shown in each memory cell denote the bit stored in that location. Su
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Quiz 5 Jon Turner 4/7/05 1. (5 points) Is the sequential circuit shown below, subject to internal hold time violations? If so, show how would you correct them. Assume that the flip flop setup time
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 5 Solutions Jon Turner 4/8/04 1. (10 points) The VHDL module defined below implements a parentheses checker, which determines if the parentheses in an incoming string of ASCII characters ar
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 5 Jon Turner 4/8/04 1. (10 points) The VHDL module defined below implements a parentheses checker, which determines if the parentheses in an incoming string of ASCII characters are balanced
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Quiz 4 Jon Turner 3/24/05 1. (6 points) Consider a sequential circuit with two inputs A, B a single output X and two state flip flops. The next-state and output equations for the circuit are D1 =
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 4 Jon Turner 3/23/04 1. (5 points) Write the output and next state equations for the sequential circuit shown below. -1- 2. (5 points) Is the sequential circuit shown below, subject to inte
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Quiz 3 Jon Turner 2/17/04 1. (4 points) Draw a logic diagram for a circuit that implements an eight input NAND function using a total of seven simple gates, where each simple gate is either a NAND
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 3 Jon Turner 2/17/04 1. (6 points) Fill in the Karnaugh map below so that it corresponds to the function F(A,B,C,D) = m(0,3,6,8,9,14), d(A,B,C,D) = m(2,5,7,10,13). Derive a product of sums
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Midterm Exam Jon Turner 3/3/05 1. (6 points) What is the dual of the expression (A + C)D + (B + D)(A + C) + AB ? What is its complement? -1- 2. (6 points) The expression AB + (A + B)C has the mint
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 2 Jon Turner 2/3/05 1. (5 points) Draw a circuit that directly implements the logic function (B + C )A + (AB + D)C . Do not simplify the expression first. Use only simple gates. -1- 2. (5 p
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 1 Jon Turner 1/27/05 1. (5 points) Consider the following pair of eight bit strings: 0011 0101 and 0011 0100. If you interpret these as eight bit binary values, what is their sum? If you in
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 2 Jon Turner 2/3/04 1. (6 points) Complete the simulation output shown below, so that it corresponds to the circuit. -1- 2. (4 points) Draw a diagram of a circuit that directly implements t
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Midterm Jon Turner 3/4/04 1. (8 points) Draw a logic diagram that directly implements the expression A(B + CD) + (C + (A+B)D) (do not simplify the expression first). How many transistors are nee
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Midterm Solutions Jon Turner 3/3/05 1. (6 points) What is the dual of the expression (A + C)D + (B + D)(A + C) + AB ? (AC)+D)(BD+AC)(A+B ) What is its complement? (AC)+D)(BD+AC)(A+B) = (A+C+D)(BD+
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab OO Patterns Introduction to ACE CS 342: Object-Oriented Software Development Lab What is ACE? OO middleware framework that implements many core design patterns for concurrent communication software Targeted for develope
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab Tools and Techniques Tools and Techniques CS 342: Object-Oriented Software Development Lab Motivation Problem Areas Approaches Tools Suggestions Introduction to Tools and Techniques David L. Levine Christopher D. Gill D
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab OO Programming with C+ Design Principles and Guidelines Overview CS 342: Object-Oriented Software Development Lab Design Principles Important design concepts Useful design principles Evaluation criteria Development Meth
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab Tools and Techniques Dynamic Diagnostic Tools (on Unix) CS 342: Object-Oriented Software Development Lab Process control Process activity Shared resources Dynamic Diagnostic Tools David L. Levine Christopher D. Gill Dep
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab Tools and Techniques Build Control CS 342: Object-Oriented Software Development Lab Why use build control? MAKE Build Control with MAKE David L. Levine Christopher D. Gill Department of Computer Science Washington Unive
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab OO Programming with C+ Background CS 342: Object-Oriented Software Development Lab Single and Multiple Inheritance in C+ David L. Levine Christopher D. Gill Department of Computer Science Washington University, St. Loui
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab OO Programming with C+ C+ Tour Topics CS 342: Object-Oriented Software Development Lab A Tour Through C+ David L. Levine Christopher D. Gill Department of Computer Science Washington University, St. Louis levine,cdgill@
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab Tools and Techniques Debugging CS 342: Object-Oriented Software Development Lab Why debug? Debugger commands dbx gdb Core dumps Debuggers David L. Levine Christopher D. Gill Department of Computer Science Washington Uni
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab Tools and Techniques Concurrent Source Control CS 342: Object-Oriented Software Development Lab What is concurrent source control? CVS and its commands Example CVS with emacs For further information Summary Source Contr
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab OO Patterns The Observer Pattern CS 342: Object-Oriented Software Development Lab Intent Define a one-to-many dependency between objects so that when one object changes state, all its dependents are notified and update
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab OO Programming with C+ Data Abstraction CS 342: Object-Oriented Software Development Lab Organizing Principle: Decide which types you want; provide a full set of operations for each type i.e., make an abstract data typ
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab OO Programming with C+ The C+ Preprocessor CS 342: Object-Oriented Software Development Lab What does the preprocessor do? Preprocessor directives For more information The C+ Preprocessor David L. Levine Christopher D.
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab OO Programming with C+ C+ Overview CS 342: Object-Oriented Software Development Lab What is C+? Origination and Evolution of C+ Why Use C+? How Does C+ Differ from Java? C+ and Java Minimal Examples Compiling C+ C+ Over
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab OO Programming with C+ C+ Objects CS 342: Object-Oriented Software Development Lab Code and data Memory allocation What is an object? How do I create an object? Object lifetime Where do I instantiate objects? Instantiat
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab OO Programming with C+ C+ Input/Output Overview CS 342: Object-Oriented Software Development Lab C+ stream classes What is a C+ I/O stream? Extractors and Inserters (shift operators) Formatting and Manipulators Lower le
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab OO Patterns Case Studies Using Patterns CS 342: Object-Oriented Software Development Lab The following slides describe several case studies using C+ and patterns to build highly extensible software Design Pattern Case S
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab The C+ STL The C+ Standard Template Library CS 342: Object-Oriented Software Development Lab What is the STL? Generic programming: why use the STL? STL overview: helper class and function templates, containers, iterator
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab Tools and Techniques Why Use Shell Scripts? CS 342: Object-Oriented Software Development Lab To automate repetitive and/or complex tasks Portable to all Unix systems, including Unix emulations on NT Why Bourne shell? cs
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab CS 342 Review Philosophy CS 342: Object-Oriented Software Development Lab Introduction to Patterns and Frameworks David L. Levine Christopher D. Gill Department of Computer Science Washington University, St. Louis flevi
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
Problem Solving Approaches CS 342: Object-Oriented Software Development Lab Why Use the Scientific Method? What is the Scientific Method? Solving Programming Problems Design Problems Debugging Problems "Problems" Problem Solving and Reporting David L. Lev
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab Tools and Techniques Why Use Perl Scripts? CS 342: Object-Oriented Software Development Lab Practical Extraction and Report Language To automate repetitive and/or complex tasks Portable to all Unix systems, NT, etc. Why
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab Tools and Techniques Source Control CS 342: Object-Oriented Software Development Lab Why use source control? RCS and its commands Example RCS with emacs For further information Summary Source Control with RCS David L. L
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab C+ Performance C+ Performance Issues Overview CS 342: Object-Oriented Software Development Lab Construction/destruction Inlining Virtual functions Static and dynamic libraries Dynamic allocation Compiler optimizations G
School: Washington University In St. Louis
Course: Object-Oriented Software Development Laboratory
CS 342: OO Software Development Lab OO Patterns The Memento Pattern CS 342: Object-Oriented Software Development Lab Intent Capture and externalize an object's internal state, without violating encapsulation, so that the object state can be restored late
School: Washington University In St. Louis
Course: Machine Learning
An Example: Text Classification each example is a text document label s the type of document (e.g. articles I will find interesting) Give algorithm based on naive bayes which is very effective Two key decision: text document needs to be converted to attri
School: Washington University In St. Louis
Course: Machine Learning
Boosting (NOTE: Ep = Epsilon) Let's begin by considering two questions 1. Suppose you are given a PAC algorithm A1, that works. For any Ep. but only for delta=1/2. That is, in poly time it outputs a hyp h with error D(h) <= E with prob >= 1/2 2. Suppose y
School: Washington University In St. Louis
Course: Machine Learning
Evaluating Hypotheses (chap 5) With enough data this is easily handled using a large validation set. Focus here is on doing this when data is limited. Two key difficulties: 1. Bias in estimate - observed accuracy over training exs often poor estimator due
School: Washington University In St. Louis
Course: Machine Learning
Computational learning theory Goal: Identify concept classes that are inherently difficult or easy to learn. For a concept class C, we want to characterize the number of training excersizes necesary to reach desired accuracy (with respect to the unknown d
School: Washington University In St. Louis
Course: Machine Learning
Two-sided and one-sided bounds Two-sided bound with N% confidence is error[s](h) - Z[N]*delta <= error[D](h) <=error[s](h) + Z[N]*delta Suppose you just want to say that error[D](h) <= x. Then you just need a one-sided bound. Let a=1-N/100 Then there is a
School: Washington University In St. Louis
Course: Machine Learning
Gradient Descent (cfw_<x->, t>, n (where <x ->, t> are the training exs) Initialize each wi to some small random value like -.05 to .05 Repeat until termination condition is met o Initialize each delta(wi) to zero o For each training ex <x->, t> Compute o
School: Washington University In St. Louis
Course: Machine Learning
Artificial Neural Networks (ANN) Robust (ie noise-tolerant) approach to approximating real-valued, discrete-valued or vector valued target functions. There are lots of things that humans do well that computers can't do well. ANN is best known algorithm fo
School: Washington University In St. Louis
Course: Machine Learning
Concept Learning and Version Spaces Concept Learning: inferring a Boolean-valued function from training examples of its input and output (supervised learning) -label is + or (boolean) -things are described by their properties ex. Regarding the property of
School: Washington University In St. Louis
Course: Machine Learning
Decision Tree Learning One of the most widely used inductive inference method. Provides method for approximate discrete-valued target functions. Nice feature of decision trees is that they can be interpreted by humans. Sample DT: can express as a disjunct
School: Washington University In St. Louis
Course: Machine Learning
Variations of basic decision tree algorithm Avoiding overfitting: Pre-pruning: stop growing the dt before it begins overfitting (before it perfectly classifies the training data) stop growing when the information gain is less than some fixed constant (E)
School: Washington University In St. Louis
Course: Machine Learning
Example for reinforcement learning: Playing Checkers Task: playing checkers (and winning) Performance: % games won against opponent (human) Experience: practice against self If given the quality of each move, then you would have supervised, on-line learni
School: Washington University In St. Louis
Course: Machine Learning
What is Machine Learning? Here is the definition given by Tom Mitchell. Machine Learning: Any computer program that improves its performance P at some task T through experience E. Example: Learn to play checkers T: play checkers & win P: % games won in to
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
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School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
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School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
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School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
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School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
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School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
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School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
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School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
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School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
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School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
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School: Washington University In St. Louis
Course: Engineering And Scientific Computing
CSE 200, Day 1, Computational Science and Engineering Hello and welcome to CSE 200. This class, Engineering And Scientific Computing is intended to teach fundamental tools and methods for the kinds of computations and simulations that you may need in your
School: Washington University In St. Louis
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School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 9 Jon Turner 4/4/02 1. (10 points) The state transition diagram shown below is for a simpler version of the arbiter circuit discussed in problem set 9. In this version, there is a fixed pri
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 10 Jon Turner 4/11/02 1. The simulation output below shows the control signals from the basic processor during the execution of five instructions. Each instruction is "boxed" for clarity. F
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 6 Jon Turner 3/27/03 1. (10 points) Is the sequential circuit defined by the VHDL code shown below a Mealy model circuit or a Moore model circuit (circle one or the other)? Draw a state dia
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 7 Jon Turner 4/10/03 1. In this problem, you are to complete the VHDL module below, so that it implements a sequential circuit with two states, up and down. If the circuit is in the up stat
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 8 Jon Turner 4/17/03 1. The simulation output below is from the basic processor running a program. The boxes outline selected instructions. Identify each of these instructions that are bein
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 8 Jon Turner 3/28/02 1. (10 points) Draw a state diagram corresponding to the VHDL module shown below. Is this VHDL for a Mealy model circuit or a Moore model circuit? What is the minimum n
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 7 Jon Turner 3/21/02 1. (6 points) Give the state transition table corresponding to the state diagram shown below. Is this state diagram for a Mealy model circuit or a Moore model circuit?
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 6 Jon Turner 2/21/02 1. The figure below shows a 4 bit lookahead comparator. If each of the complex gates were replaced by simple gates, what would be the worst-case delay through this circ
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 5 Jon Turner 2/14/02 1. (6 points) Show how to implement the expression (A + C)D + B D using an 8:1 multiplexor plus one inverter. 2. (4 points) How many simple gates are needed to implemen
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 5 Jon Turner 3/20/03 1. (10 points) The table shown below is the state transition table for a sequential circuit with two states, one input A and one output X. Give the next state and outpu
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 4 Jon Turner 2/20/03 1. (10 points) What output value is produced by the circuit defined by the VHDL specification shown below, when the input value is 1100? What unsigned numerical values
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 4 Jon Turner 2/7/02 1. (6 points) Give a minimal product-of-sums expression for AC + A BD + BC. 2. (4 points) How many transistors are needed to implement the circuit shown below in CMOS te
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 3 Jon Turner 2/13/03 1. (6 points) List the minterms in the expression A B D + B(CD + A C). If you wish, you may list them numerically. How many gates of each type are required to implement
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 3 Jon Turner 1/31/02 1. (5 points) Find the complement of the expression BC + (A + C)B D and write it in minimal sum-of-products form. 2. (5 points) Simplify the logic function F(A,B,C) = m
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 2 Jon Turner 1/24/02 1. (10 points) How many simple gates of each type are needed to implement the expression shown below (without simplification)? (A + BC)(B + CD) + A(CD + BCD) Use Boolea
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 1 Jon Turner 1/24/03 1. (4 points) What is the hexadecimal representation of the decimal value 189? Express -42 as an eight bit twos-complement value. -1- 2. (6 points) If our basic process
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 2 Jon Turner 1/30/03 1. (5 points) Draw a circuit that directly implements the logic function (A + C)B + D(AB + C). Do not simplify the expression first. -1- 2. (5 points) Give expressions
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Mid-Term Exam Jon Turner 3/13/03 1. (6 points) List all the minterms for the expression (B + A)C + AC + BC. List the maxterms for the expression. -1- 2. (5 points) Show that the following Boolea
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 1 Jon Turner 1/17/02 1. (4 points) What is the pattern of bits used to represent the integer 937 in BCD? 2. (6 points) If our basic processor begins execution with the first instruction sho
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Mid-Term Exam Jon Turner 2/28/02 1. (5 points) Compute the difference: 011011 001101 using six bit binary arithmetic, by taking the 2s complement of the second operand and then adding. 2. (10 po
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Mid-Term Exam Solutions Jon Turner 2/28/02 1. (5 points) Compute the difference: 011011001101 using six bit binary arithmetic, by taking the 2s complement of the second operand and then adding.
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Mid-Term Exam Solutions Jon Turner 3/13/03 1. (6 points) List all the minterms for the expression (B + A)C + AC + BC. Expanding the expression gives BC + AC + AC + BC = ABC + ABC + ABC + ABC + A
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Final Exam Jon Turner 4/30/02 1. (5 points) Simplify the following expression using the basic identities of Boolean algebra. (A + B)C + AB)BD -1- 2. (14 points) Find a minimum sum of products ex
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Final Exam Jon Turner 5/6/03 1. (10 points) How many simple gates of each type (and, or, inverter) are needed to directly implement the expression A(B+CD)+(A+CD). Find the simplest equivalent su
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Final Exam May 4, 2001 You may have one sheet of notes. No calculators. Write in the spaces provided. Be neat. 1. (4 points) Assuming 8 bit words, what is the binary representation of 79? What is the hexadecimal representation of 79? What is the
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Final Exam Solutions May 4, 2001 You may have one sheet of notes. No calculators. Write in the spaces provided. Be neat. 1. (4 points) Assuming 8 bit words, what is the binary representation of 79? 0100 1111 What is the hexadecimal representatio
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Final Exam Spring 2000 You may use one page of notes. No calculators. Write in the spaces provided. Be neat. 1. (10 points) Write the machine language instructions needed to implement each of the lines of pseudo-code shown below. The list of mac
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Final Exam Solutions Jon Turner 5/6/03 1. (10 points) How many simple gates of each type (and, or, inverter) are needed to directly implement the expression A(B+CD)+(A+CD). 3 ANDs, 3 ORs and 2 i
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 - Exam 2 4/23/2001 1. (10 points) Draw a state diagram for the sequential circuit shown below. W D Q A >C Q D E Clk Q Y Z B >C Q -1- 2. (10 points) Answer the following questions, in connection with the circuit in problem 1. Assume that the flip
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Final Exam Solutions Jon Turner 4/30/02 1. (5 points) Simplify the following expression using the basic identities of Boolean algebra. (A + B)C + AB)BD = (AC + BC + AB)BD = ABCD + ABD = ABD(C +
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 - Exam 1 Solutions 3/5/2001 1. (6 points) Using 40 bits, how many different integers can be represented in (a) binary 2 40 (b) BCD 10 10 (c) 8-bit ASCII? 10 5 2. (12 points) The simulation output on the next page is from an execution of the simp
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 - Exam 2 Solutions 4/23/2001 1. (10 points) Draw a state diagram for the sequential circuit shown below. W D Q A >C Q D E Clk Q Y Z B >C Q AB 00 01 10 11 00 00 01 01 10 10 11 11 EW D ADB 0x 00 0x 00 0x 00 0x 00 10 01 11 11 10 11 11 01 10 00 11 1
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 - Exam 1 3/5/2001 1. (6 points) Using 40 bits, how many different integers can be represented in (a) binary, (b) BCD, (c) 8-bit ASCII? -1- 2. (12 points) The simulation output on the next page is from an execution of the simple processor introdu
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Final Exam Solutions Spring 2000 You may use one page of notes. No calculators. Write in the spaces provided. Be neat. 1. (10 points) Write the machine language instructions needed to implement each of the lines of pseudo-code shown below. The l
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Exam 2 April 13, 2000 You may have one sheet of notes. No calculators. Write in the spaces provided. Be neat. 1. (10 points) Several flip flops and latches are shown below. Identify each one completely (e.g. Master-Slave SR flip flop) and label
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Exam 2 Solutions April 13, 2000 You may have one sheet of notes. No calculators. Write in the spaces provided. Be neat. 1. (10 points) Several flip flops and latches are shown below. Identify each one completely (e.g. Master-Slave SR flip flop)
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Exam 1 Spring 2000 No books, no notes, no calculators. Write in the spaces provided. Be neat. 1. (5 points) What is the binary representation of 678? What is the octal representation? Hexadecimal? 678 = 512 + 166 166 = 128 + 38 38 = 32 + 6 6= 4+
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Exam 1 Spring 2000 No books, no notes, no calculators. Write in the spaces provided. Be neat. 1. (5 points) What is the binary representation of 678? What is the octal representation? Hexadecimal? 2. (5 points) Use a Karnaugh map to find the sim
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Quiz 7 Jon Turner 4/26/05 1. (4 points) Consider a processor with a 2-way set associative cache with a total of 32 words (16 per bank), used for data only. Suppose that a program being executed ha
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Quiz 6 Jon Turner 4/14/05 1. (5 points) Is the sequential circuit shown below, subject to internal hold time violations? If so, show how would you correct them (be specific). Assume that the flip
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 7 Jon Turner 4/27/04 1. (4 points) In the program for the basic processor shown below, the loop is executed 10 times. How many times are instructions retrieved from memory during the execut
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 6 Jon Turner 4/20/04 1. (4 points) The diagram below shows a memory array containing 16 words of 4 bits each. The values shown in each memory cell denote the bit stored in that location. Su
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Quiz 5 Jon Turner 4/7/05 1. (5 points) Is the sequential circuit shown below, subject to internal hold time violations? If so, show how would you correct them. Assume that the flip flop setup time
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 5 Solutions Jon Turner 4/8/04 1. (10 points) The VHDL module defined below implements a parentheses checker, which determines if the parentheses in an incoming string of ASCII characters ar
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 5 Jon Turner 4/8/04 1. (10 points) The VHDL module defined below implements a parentheses checker, which determines if the parentheses in an incoming string of ASCII characters are balanced
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Quiz 4 Jon Turner 3/24/05 1. (6 points) Consider a sequential circuit with two inputs A, B a single output X and two state flip flops. The next-state and output equations for the circuit are D1 =
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 4 Jon Turner 3/23/04 1. (5 points) Write the output and next state equations for the sequential circuit shown below. -1- 2. (5 points) Is the sequential circuit shown below, subject to inte
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Quiz 3 Jon Turner 2/17/04 1. (4 points) Draw a logic diagram for a circuit that implements an eight input NAND function using a total of seven simple gates, where each simple gate is either a NAND
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 3 Jon Turner 2/17/04 1. (6 points) Fill in the Karnaugh map below so that it corresponds to the function F(A,B,C,D) = m(0,3,6,8,9,14), d(A,B,C,D) = m(2,5,7,10,13). Derive a product of sums
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Midterm Exam Jon Turner 3/3/05 1. (6 points) What is the dual of the expression (A + C)D + (B + D)(A + C) + AB ? What is its complement? -1- 2. (6 points) The expression AB + (A + B)C has the mint
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 2 Jon Turner 2/3/05 1. (5 points) Draw a circuit that directly implements the logic function (B + C )A + (AB + D)C . Do not simplify the expression first. Use only simple gates. -1- 2. (5 p
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 1 Jon Turner 1/27/05 1. (5 points) Consider the following pair of eight bit strings: 0011 0101 and 0011 0100. If you interpret these as eight bit binary values, what is their sum? If you in
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Quiz 2 Jon Turner 2/3/04 1. (6 points) Complete the simulation output shown below, so that it corresponds to the circuit. -1- 2. (4 points) Draw a diagram of a circuit that directly implements t
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CS/EE 260 Digital Computers: Organization and Logical Design Midterm Jon Turner 3/4/04 1. (8 points) Draw a logic diagram that directly implements the expression A(B + CD) + (C + (A+B)D) (do not simplify the expression first). How many transistors are nee
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Midterm Solutions Jon Turner 3/3/05 1. (6 points) What is the dual of the expression (A + C)D + (B + D)(A + C) + AB ? (AC)+D)(BD+AC)(A+B ) What is its complement? (AC)+D)(BD+AC)(A+B) = (A+C+D)(BD+
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
JEE2600 Homework Assignment #8 Problems due Monday, November 15th. Show your work on all problems. 1. Using the following state diagram, create a sequential circuit that will 000 /0 001 /0 X 011 /0 111 /0 QC QBQA 110 /1 X' implement this state diagram and
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
JEE2600 Homework Assignment #10 Solutions 1. Rework test 1 problems (Each problem is worth half of what it was worth on the test). Test answers are posted on the syllabus page. 2. Draw a circuit that implements the following RTL statement using 1-bit regi
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
JEE2600 Homework Assignment #7 Solutions Problems due Monday, November 8th. Show your work on all problems. 1. Problem 7.12 (6 pts) Excitation and output equations: D1 = Q1 + Q2 D2 = Q2X Z = Q1 + Q2 Excitation/transition table; state/output table: 2. Prob
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
JEE2600 Homework Assignment #9 Solutions 1. Assuming ideal timing (propagation delays and setup/hold times are zero) complete the following timing diagram for the 74x194 shift register. Read p.730 for a clarification on the functionality of this chip. (10
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
JEE2600 Homework Assignment #5 Problems due Monday, October 18th. Show your work on all problems. 1. Design an 8:3 encoder that acts like a priority encoder for the lower four inputs, but for the four higher priority inputs both the input and the 7's comp
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
JEE2600 Homework Assignment #4 Solutions 1. Starting at t = 0, draw two timing diagrams for the following schematic when IN changes from 0 to 1 and 1 to 0 using the following propogation delays: A 15ns 12ns tpLH tpHL B 10ns 10ns C 9ns 9ns Draw the timing
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
JEE2600 Homework Assignment #3 Solutions 1. Problem 4.14 a & b. List all prime and essential prime implicants/implicates. (4 pts. ea.) Prime Implicants: XY, Z Essential Prime Implicants: XY, Z Distinguished 1 cells are gray , Prime Implicants: W'Y'Z, XYZ,
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
JEE2600 Homework Assignment #6 Solutions 1. Problem 7.4 (4 pts) 2. Problem 7.5 (4 pts) The latch oscillates if S and R are negated simultaneously. Many simulator programs will exhibit this same behavior when confronted with such input waveforms. 3. Assumi
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
JEE2600 Homework Assignment #1 Solutions 1. 1. Problem 1.6 (3 pts) AB 00 01 10 11 C 0 1 1 1 The same function is performed by a single 2-input OR gate. 2. Problem 3.5 (1pt) False. The outputs are the same, since an OR gate with inverted inputs is the same
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
JEE2600 Homework Assignment #2 Solutions 1. Do the following operations in binary. Convert the result back into decimal. ( 2 pts. ea.) a. 9 x 12 1001 x 1100 0000000 0000000 0100100 1001000 11011002 => 10810 b. 3 x 10 0011 x 1010 0000000 0000110 0000000 00
School: Washington University In St. Louis
CSE 200 Spring 2008, HW 9 due date: April 1, in or before class. (just to remind you the hw submission policy 1) 30% if submitted after the class but on the same due day (on Tuesday) 2) 50% if submitted the next day (on Wednesday) 3) no homework wil
School: Washington University In St. Louis
CS 201 Formal Foundations of Computer Science November 29, 2000 Fall Semester, 2000 Homework Assignment 10 Due Date: December 6 Quiz on Dec 4 Practice Exercises 1. For each relation given below, indicate whether the binary relation R over A i.e.
School: Washington University In St. Louis
CSE 441T/541T Advanced Algorithms Fall Semester, 2004 HW 3 Practice Problems October 12, 2004 Here are LOTS of practice problems. For preparing for HW 3, problems 1-5 are good and answers are included for those. Youll nd the rest useful both for HW
School: Washington University In St. Louis
CSE 441T/541T Advanced Algorithms Homework 0 Practice Your Proofs! Assigned: August 27, 2008 Due Date: None Based on past experience, an important prerequisite for this course is the ability to create and write correct proofs and to realize when y
School: Washington University In St. Louis
CS/EE 260 Homework 5 Solutions Spring 2000 1. (MK 3-23) Construct a 10-to-1 line multiplexer with three 4-to-1 line multiplexers. The multiplexers should be interconnected and inputs labeled so that the selection codes 0000 through 1001 can be dire
School: Washington University In St. Louis
CS 441T 539T: Advanced Algorithms September 13, 2001 Fall Semester, 2001 Due Date: September 27 Homework Assignment 2 When asked to give an algorithm, you are expected to give a clear description of the algorithm, prove it is correct, and analyze
School: Washington University In St. Louis
CSE 441T/541T Advanced Algorithms Fall 2008 Homework 1: Greedy Algorithms Assigned: September 3, 2008 Due Date: September 17, 2008 Whenever you are asked to give an algorithm for a problem, I expect you to do all of the following: 1. give a clear,
School: Washington University In St. Louis
CS 241 Algorithms and Data Structures March 23, 1999 Spring Semester, 1999 Due Date: April 1 no joke Homework 4 In each problem in which you are asked to provide an algorithm you should give a clear high-level description of the algorithm make it
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Lab 4 Jon Turner Due 4/1/2013 Review and follow the general instructions from lab 1. In this lab, youll be designing and implementing a circuit that implements the classic 15-puzzle game (see pict
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Lab 5 Jon Turner Due 5/1/2014 Review and follow the general instructions from lab 1. This lab consists of several parts. In the first part, you will be add the following three instructions to the
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Jon Turner Lab 1 Solution 1/28/2014 Part A (20 points). Paste the VHDL for your modified calculator below. Highlight your modifications to the code by making them bold. Note that the next paragrap
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Lab 3 Jon Turner Due 3/4/2014 Review and follow the general instructions from lab 1. In this lab, youll be designing and implementing a stack-based calculator. There will be two parts to this circ
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Lab 2 Jon Turner Due 2/18/2014 Review and follow the general instructions from lab 1. In this lab, you will be designing and implementing a patternMatcher circut. This circuit will detect strings
School: Washington University In St. Louis
Course: Introduction To Digital Logic And Computer Design
CSE 260 Digital Computers: Organization and Logical Design Lab 1 Jon Turner Due 1/28/2014 General notes for labs. The labs are intended to give you the opportunity to apply what youve learned in the course to larger problems and to gain some experience wi
School: Washington University In St. Louis
Course: Engineering And Scientific Computing
Lab 12: Monte Carlo fun! Monte-Carlo Integration extravaganza! In this problem you have to compute the area of complex surfaces. Consider a surface made as a sphere with a cylinder cut through it. The sphere is a unit sphere centered at the origin. The cy
School: Washington University In St. Louis
Course: Engineering And Scientific Computing
Lab 10: Variable length pendulae This lab will follow up from class. In class we wrote the procedure DPenddT, and visualizePend function dPdT = dPenddT(t,p) u = p(1); v = p(2); g = -9.8; L = 1; uPrime = v; vPrime = (g/L) * sin(u); no friction dPdT = [uPri
School: Washington University In St. Louis
Course: Engineering And Scientific Computing
Lab 9: Choosing parameters for physical simulations Last lab we simulated a set of springs attached to two anchor points, and let the system evolve to a steady state. When that steady state is reached, the points should lie along a curve called a "catenar
School: Washington University In St. Louis
Course: Engineering And Scientific Computing
Lab 11: Damped, driven pendulae This lab will follow up from last weeks lab. Last week we simulated a pendulum and saw how it changes its motion as it is shortened, and then tried to make a schedule to shorten it without having it spin around. This time w
School: Washington University In St. Louis
Course: Engineering And Scientific Computing
Lab 8: Back to physical simulations Several labs ago, we simulated a block on a spring attached to a wall, and we saw how that block acted if we pulled. This week we are going to model an elastic string as a large collection of stones, attached to each ot
School: Washington University In St. Louis
Course: Engineering And Scientific Computing
Lab 7: NIM is played with two players and a pile of coins. The players take turns removing coins from the pile. On each turn, a player must take one, two, or three coins from the pile. The player who takes the last coin loses. You are going to write a GUI
School: Washington University In St. Louis
Course: Engineering And Scientific Computing
Lab 1: Mandelbrot Set Lab idea from John Hughes, professor of Computer Science at Brown. Lab Goals: 1. Programing construct: iterations 2. Programing tool: .m files 3. Mathematical concepts: limits of iterative functions In class we talked about matlab's
School: Washington University In St. Louis
Course: Engineering And Scientific Computing
Lab 5: Intro to physical simulation Today we are going to break from things we've been talking about in class and look at simulating physical processes. In particular, we are going to write functions which simulate simple Newtonian physics. In particular,
School: Washington University In St. Louis
Course: Engineering And Scientific Computing
Lab 4: In class on tuesday we talked about solving a matrix equation to fit a line to a collection of points. Today we are going to do the same thing in order to fit a curve to a collection of points. In particular, we will consider polynomial curves - th
School: Washington University In St. Louis
Course: Engineering And Scientific Computing
Lab 6: Physical Simulation II Starting with this lab, there will be only one *required* checkpoint (at the end), and several optional checkpoints that I hope you will use if you aren't getting the expected results. Today we are going to solve a system of
School: Washington University In St. Louis
Course: Engineering And Scientific Computing
Lab 3: Linear Regression and Functions with Multiple Outputs In class on tuesday we talked about matrix operations. Today we are going to practice with some of these, then apply them to the problem of linear regression. Regression (or fitting, or least sq
School: Washington University In St. Louis
Course: Engineering And Scientific Computing
Lab 2: Matrix Manipulation and Fluid Diffusion In class we talked about ways of organizing our approach to a problem, and also a collection of new matlab commands. Today we are going to start practicing with arrays. Problems 1. Given nonzero integers n an