EE 231
Fall 2015
EE 231 Lab 8
Computer Control Unit
You are on your way to designing your first computer, but first you need build the control
unit. A conceptual block diagram of a simple computer is shown in Figure 1. In previous
labs you have already de
EE 231
Fall 2015
EE 231 Lab 1
Introduction to Verilog HDL and Quartus
In this lab you will design simple circuits by programming the field-programmable gate array
(FPGA). At the end of the lab you should be able to understand the process of programming a
EE 231
Fall 2015
EE 231 Lab 9
Build a Computer
A conceptual block diagram of a simple computer is shown in Figure 1. In previous labs
you have already designed the Addr_Mux, the ALU, the control unit and the required
registers. In this lab you will put al
E 231
EEE 231
F a l l Fall
2 0 12015
0
EE 231 Lab 4
E E 231 L ab 5
Arithmetic Logic Unit
A r ith m etic L o g ic U n it
The heart of every computer is an Arithmetic Logic Unit (ALU). This is the part of the computer
T h e performs
h e a r t o f e arithmet
EE 231
Fall 2015
EE 231 Lab 2
Decoders and Multiplexers
1.Lab
1.1. Place a block of 8 DIP switches on your proto-board, Figure 1.
Figure 1: Dip Switches
1.2. Connect each lead on one side to VCC. You can use an external power or the VCC_SYS
provided on yo
EE 231
Fall 2015
EE 231 Lab 0
HCMOS Logic Family
1.Lab
1.1Basic Behavior of HCMOS Logic Family
1.1.2. Use the datasheet to connect a 7404 IC.
1.1.3. Connect the input to GND and check that the output is a logic 1 using the logic
probe. After, connect the
EE 231
Fall 2015
EE 231 Lab 6
Debouncing Switches
1.Lab
1.1.Switch Bounce
1.1.1. Build the switch in Figure 1. For now, just use a wire as the switch. Plug the wire
into GND to bring OUT (the switch output) low, alternatively, unplug it to bring
OUT high.
EE 231
Fall 2015
EE 231 Lab 7
Sequential Circuits:
How Fast Are You?
1.Lab
1.1.Simulate your Verilog program and make sure it works as planned.
1.2.Wire your double 7-segment display and test your counter code.
1.3.Wire two debounced switches. One will be
EE 231
Fall 2015
EE 231 Lab 5
Registers
1.Lab
1.1.Objective
1.1.1.You will implement five different 8-bit registers: PC (Program Counter), MAR
(Memory Addressing Register), OUT (Output), ACCA (Accumulator A), and INST
(Instruction Register). In addition,
EE 231
Fall 2015
EE 231 Lab 3
Adder/Subtractor
In the previous lab you have defined a half adder by using primitive gates. As the design
becomes more and more complex, it is convenient to create separate modules and then
combine them in one file. For exam
EE 211-02: Circuits and Signals I & ES 332-02: Electrical Engineering
Fall 2015
Classroom: MSEC 195
Class time: MWF, 11:00am-11:50am
Instructor: Dr. Seda Senay
Office: Workman 219
Phone: 575-835-6800
E-mail: [email protected]
Office hours: W&Th, 14:00-15:30
EE 322 Analog Electronics, Spring 2010
Exam 2 March 31, 2010
Solution
Rules: This is a open book test. You may use the textbooks as well as your notes. The exam
will last 50 minutes. Each numbered problem counts equally toward your grade.
LCR circuit
R
L
EE 322 Advanced Analog Electronics, Spring 2010
Homework #3 solution
SS 13.5. In a particular oscillator characterized by the structure of Fig 13.1, the
frequency-selective network exhibits a loss of 20 dB and a phase shift of 180 at
0 . What is the minim
EE 322 Advanced Analog Electronics, Spring 2010
Homework #2 solution
HH 6.8
Theoretically, a linear regulator delivers on the output up to the same current as it draws
on the input. The maximum delivered output power is therefore
Pout,max = Vout Iin .
The
EE 322 Advanced Analog Electronics, Spring 2010
Homework #1 solution
HH 6.3. Design a 723 regulator whith outboard pass transistor and foldback
current limiting to provide up to 1.0 amp when the output is at it regulated
value of +0.5 V, but only 0.4 amp
EE 322 Analog Electronics, Spring 2010
Exam 4 May 12, 2010
Solution
1. Linear regulator
The LM7805 is a linear regulator with a xed output of 5 V and up to 1 A.
Design a voltage regulator using the LM7805 and a external pass transistor, in
which the pass
EE 322 Advanced Analog Electronics, Spring 2010
Homework #4 solution
SS 13.34. Figure P13.34 shows a monostable multivibrator circuit. In the stable
state, vo = L+ , vA = 0, and vB = Vref . the circuit can be triggered by applying
a positive input pulse o
EE 322 Advanced Analog Electronics, Spring 2010
Homework #6 solution
SS 12.9. A third-order low-pass lter has transmission zeros at = 2 rad/s and
= . Its natural modes are at s = 1 and s = 0.5 j 0.8. The DC gain is
unity. Find T (s).
We construct the tra
EE 322 Advanced Analog Electronics, Spring 2010
Homework #11 solution
SS 7.1. For a NMOS dierential pair with a common-mode voltage vCM applied,
as shon in Fig. 7.2, let VDD = VSS = 2.5 V, knW/L = 3 mA/V2 , Vtn = 0.7 V,
I = 0.2 mA, RD = 5 k, and neglect c
EE 322 Advanced Analog Electronics, Spring 2010
Homework #10 solution
SS 8.73. An amplier has a dc gain of 105 and poles at 105 Hz, 3.16 105 Hz, and
106 Hz. Find the value of and the corresponding closed-loop gain, for which a
phase margin of 45 is obtain
EE 322 Advanced Analog Electronics, Spring 2010
Homework #9 solution
SS 12.48. It is required to design a third-order low-pass lter whose |T | is equiripple in both the passband and the stopband (in the manner showin in Fig. 12.3,
except that the response
EE 322 Advanced Analog Electronics, Spring 2010
Homework #7 solution
SS 12.13. Calculate the value of attenuation obtained at a frequency 1.6 times
the 3-dB frequency of a seventh-order Butterworth lter, and compare it to the
rst order lter.
The 3-dB freq
EE 322 Advanced Analog Electronics, Spring 2010
Homework #8 solution
HH 9.5. Show that these choices of lter components actually give a loop gain
of magnitude 1.0 at f2 = 2.0 Hz.
The magnitude of the loop gain expression on page 649 is
|Gloop | = KP
22
KV
EE 554 Fall 2011
EE 554 Homework Chapter 6
6.7 Design a digital filter by applying the bilinear transformation to the analog
(Butterworth) filter
1
=
+ 2 +1
With T = 0.1s. Then apply prewarping at the 3-dB frequency.
6.13 Design a deadbeat controller for
EE 554 Fall 2011
EE 554 Homework Chapter 5
5.13 Consider the system
=
1
+1
And apply the Ziegler-Nichols procedure to design a PID controller. Obtain the response
due to a nit step input as well as a step disturbance signal.
5.14 Write a computer program
EE 554 Fall 2011
EE 554 Homework Chapter 4
4.6 Use the Routh-Hurwitz criterion to find the stable range of K for the closed-loop
unity feedback systems with loop gain
(a)
=
(b)
=
.
.
.
.
.
4.16 Simulate the closed-loop systems shown in Problem 4.6 with a
EE 554 HW3
Fall 2010
(20 points) 5.4 Consider the system in 5.3(ii) with a required steady-state error of 20%, and an adjustable PI
controller zero location. Show that the corresponding closed-loop characteristic equation is given by
1
s+a
1+ K
=0
s ( s +
EE 554 Fall 2011
EE 554 Homework Chapter 3
3.3 Many chemical processes can be modeled by the following transfer function:
=
+1
Where K is the gain, is the time constant and Td is the time delay. Obtain the T.F.
Gzas(s) for the system in terms of the syste
EE 554 HW2
Fall 2010
(10 points) Find the equivalent sampled impulse response sequence and the equivalent z-transfer function for the
cascade of the two analog systems with sampled input
H 1 ( s) =
1
s+6
H 2 (s) =
10
s +1
(a) If the systems are directly c
EE 554 Fall 2011
EE 554 Homework Chapter 2
2.6 Use the linearity of the z-transform and the transform of the exponential function to
obtain the transforms of the discrete-time functions.
(a) sin (
)
(b) cos (
)
2.8 Find the inverse transforms of the follo