Issue PAPER
august 2012 iP:12-06-B
Wasted: How America Is Losing Up to 40
Percent of Its Food from Farm to Fork to Landfill
Author
Dana Gunders
Natural Resources Defense Council
Getting food from the farm to our fork eats up 10 percent of the total U.S. e

Counters
I.
(CST 170)
Counters
A.
A predictable series of binary states.
1.
2.
3.
4.
States can be ascending sequential e.g. 0000 to 1111
States can be descending sequential e.g. 1111 to 0000
States can be non-sequential
a)
Count by 2s or 3s
States can ap

Counters
I.
Sequential Counter Design
II.
(CST 170/Rev. 7/11/2013/Kohut)
Problem
A.
III.
Step 1
A.
2
4
8
10
IV.
Design a counter that will count 2, 4 , 8, 10
0
0
1
1
Write down the count sequence in binary.
0
1
0
0
1
0
0
1
0
0
0
0
Step 2
A.
Draw a table s

Flip-Flops
I.
(CST 170)
Multivibrator Circuits
A.
Contains two opposite outputs
B.
Three Types
1.
2.
3.
C.
Astable
1.
D.
Astable (also called clocks)
Monostable (also called one-shots)
Bistable (also called flip-flops)
The outputs of an astable multivibra

Decoders and Encoders
(CST 170/Rev. 6/26/2013/Kohut)
NOTE: Before starting this material you should download the file named 08_Multisim
files.zip from Angel and unzip them.
I.
Decoders
A.
To detect the presence of a specific combination of bits on
its inp

Quine-McClusky
Quine-McClusky Reduction Techniques
I.
Quine-McClusky
A.
B.
Can be used for more than 4 variables
C.
II.
Another systematic method for achieving a minimized expression.
Algorithm can be programmed in C# or C+. MultiSim 10, and later,
uses Q

Introduction/Basic gates (CST 170/Rev. 6/12/2013)
I. Types of information
A. Analog
1. continuous, involves estimation
2. Clock with hands, slide rule
NOTE: You should complete the
reading assignment listed in the
course outline before reviewing
this cond

Multiplexers/Demultiplexers
I.
(CST 170)
Multiplexer
A.
Definition
1.
A circuit that switches digital data from several input lines to a
single output line.
2.
We know that the following circuit will enable one and only
one of the four outputs. We called

Adders and Comparators
I.
(CST 170)
Adders
A.
Half Adder
1.
The half adder accepts two binary digits on its inputs and produces
two binary digits on its outputs, a sum bit and a carry bit.
0
+0
0
2.
0
+1
1
1
+0
1
1
+1
10
Use the information above to devel

Boolean Algebra
I.
Boolean Algebra (part II)
II.
(CST 170/Rev. 6/18/2013/Kohut)
Rules for Boolean Algebra
Reference Sheet
(Keep handy)
A 1 = A
A 0 = 0
Union
A + 1 = 1
A + 0 = A
Tautology
A A = A
A + A = A
Complement
A A = 0
A + A = 1
A = A
Intersection
Th

Karnaugh Maps
(CST 170)
I. Karnaugh Maps
A. A systematic method for simplifying and manipulating Boolean expressions
B. For each possible combination of input variables, there is one cell on the
map.
C. Karnaugh maps are arranged in a specific way to take

Computer Logic, CST 170
Module 7
Adders and Comparators
Introduction
In Module #6, you learned about some very important features of combinational logic circuits
and how NAND and NOR gates could be used as universal gates. They are considered universal
be

Boolean Algebra
I.
Boolean Algebra (part I)
II.
(CST 170/Rev. 6/18/2013/CST)
Rules for Boolean Algebra
Reference Sheet
(Keep handy)
A 1 = A
A 0 = 0
Union
A + 1 = 1
A + 0 = A
Tautology
A A = A
A + A = A
Complement
A A = 0
A + A = 1
A = A
Intersection
The r

SOP Forms
(CST 170)
I. SOP Standard form
A. An expression is in Standard form when each product term includes all of the
variables in the domain of the expression.
AB + BC is not in standard form
ABC + ABC + ABC is in standard form for a domain of three v

See discussions, stats, and author profiles for this publication at: https:/www.researchgate.net/publication/26834291
Biogas production: Current state and
perspectives
Article in Applied Microbiology and Biotechnology September 2009
DOI: 10.1007/s00253-00

Combinational Logic
(CST 170)
Combinational Logic
*Nothing in this document is submitted to me for the course. This material is designed to teach you
concepts and the suggested work is for your benefit only.
I.
Combinational Logic Vs. Sequential Logic
A.