4
COMBINATIONAL
LOGIC DESIGN
PRINCIPLES
E X E R C I S E
S O L U T I O N S
4.2
T3:
T2:
X
X+1
=
1
X
X+X
=
X
0
1
1
1
=
=
1
1
0
1
0
1
=
=
0
1
X
XX
=
X
0
1
0
1
=
=
0
1
X
Y
X+Y
=
Y+X
0
0
1
1
0
1
0
1
0
1
1
1
=
=
=
=
0
1
1
1
4.3
T3
4.4
T6
41
42
DIGITAL CIRCUITS
4
EE365
Adv. Digital Circuit Design Clarkson University
Lecture #6 Timing and Related Design Considerations
Topics
Signal Naming Conventions -Buses Timing Diagrams Data Book Reference Timing Specifications Timing Hazards
Lect #6
Rissacher EE365
Buses
A gr
2
NUMBER SYSTEMS AND CODES
E X E R C I S E 2.1 (a) (c) (e) (g) (i) 2.3 (a) (b) (c) (d) (e) (f) 2.5 (a) (c) (e) (g) (i)
S O L U T I O N S (b) (d) (f) (h) (j) 174003 8 = 1111100000000011 2 67.24 8 = 110111.0101 2 F3A5 16 = 1111001110100101 2 AB3D 16 = 10101
7
Sequential
Logic Design Principles
E X E R C I S E
S O L U T I O N S
7.2
S
R
Q
QN
7.3
The latch oscillates if S and R are negated simultaneously. Many simulator programs will exhibit this same
behavior when confronted with such input waveforms.
S
R
Q
QN
Homework # 2 EE365
1) Textbook Problem 5.28 on page 458
2) Textbook Problem 5.40 on page 460
3) Build a 4-bit Ripple Subtractor out of 74x999 (fuller adders) and inverters.
(see figure 5-88 and pages 432-434) 4) From memory, define the function of the fol
Quiz #5 Solution
EE365
Clarkson University
Summer 2003
An adder and subtractor have two differences:
A subtractor has one input inverted
The carry-ins and carry-outs can be considered active-low
To design a circuit that does both addition and subtractio
EE 365 Advanced Digital Circuit Design Summer Session #1, 2003 CAMP 175, 1:15 - 2:45 daily www.clarkson.edu/class/ee365 I. Course Description An advanced course in digital circuit design, this course begins with a review of switching algebra and combinati
Quiz #6 EE365 Clarkson University Summer 2003
Name: _ Student #: _ Show how to build a flip-flop equivalent to the 74x109 positive edge-triggered JK' flip-flop using a 74x74 positive-edge-triggered D flip-flop, NAND gates and inverters.
Quiz #4 EE365 Clarkson University Summer 2003
Name: _ Student #: _
You are given two 74LS138 3-to-8 decoders and one 74LS30 8-input NAND gate. Build a circuit to realize the following function:
F = W , X ,Y , Z (0,1,2,3,5,7,11,13)
EE365
Adv. Digital Circuit Design Clarkson University
Lecture #7 Intro to MSI PLDs and Decoders
Topics
MSI Intro PLDs Decoders
Lect #7
Rissacher EE365
Role of MSI Components in Logic Design
Gates are the fundamental building blocks of logic - the "atoms
EE365
Adv. Digital Circuit Design Clarkson University
Lecture #2 Boolean Laws and Methods
Boolean algebra
a.k.a. "switching algebra"
deals with boolean values - 0, 1
Positive-logic convention
analog voltages LOW, HIGH -> 0, 1
Signal values denoted by
EE365
Adv. Digital Circuit Design
Clarkson University
Lecture #1
Course Outline
Number Systems
Syllabus
No mid-course exams (only final exam)
Design Problems heavily weighted
Optional homeworks
Quizzes (every few days) correspond to HWs
Textbook: doe
EE365
Adv. Digital Circuit Design Clarkson University
Lecture #3 Combinational Logic
Combinational-Circuit Analysis
Combinational circuits - outputs depend only on current inputs (not on history). Kinds of combinational analysis:
exhaustive (truth table
Quiz #2 Solution
EE365
Clarkson University
Summer 2003
Yes, it is correctly designed.
Here is the truth table:
A
0
0
1
1
B
0
1
0
1
Q1
off
on
off
on
Q2 Q3 Q4 Q5 Q6 Z
on off on on off 1
off off on off on 1
on on off on off 0
off on off off on 1
Thus:
Z = (A
Quiz #3 Solution EE365 Clarkson University Summer 2003
Question: Compute the overall fanout for 74VHCT devices driving 74AS devices. Solution: For each interfacing situation, we compute the fanout in the LOW state by dividing IOLmax of the driving gate by