CSE220 Spring 2015
Practice Problems #10
Problem 1: Show the forwarding paths and stalls needed to execute the following instructions assuming
the beq is taken the rst time but not the second. Attempt
CSE220 Spring 2015
Practice Problems #9
Problem 1: Using the abstract pipelined datapath gure (as shown below, handout on piazza), show
the forwarding paths and stalls needed to execute the following
CS220 Spring 2015
Practice Problems #8
Problem 1: Assuming the following timings for the components of the datapath. All other components have no
delay.
Data/Instruction Memory Read: 200ps
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CSE320 Lecture 18-19
MIPS Multicycle Datapath
The single cycle implementation of the MIPS datapath was inefficient.
o Clock cycle time is dictated by the longest instruction. The rest of the instructi
CSE220 Lecture 23
MIPS Pipelining Basics
What we have seen so far is a very simplified approach to the execution of MIPS instructions.
We fetch an instruction, decode it, and execute it completely bef
CSE220 Lecture 24
MIPS Pipelining Hazards
Hazards are situations, caused by the sequence of MIPS instructions or the hardware, that prevent or
complicate the execution of the next instruction in the p
CSE220 Lecture 25
MIPS Pipelining Hazards - continued
Control Hazards
Typical execution of instructions is one after another in memory. However, branch and jump instructions
allow for the linear execu
Performance
Measure, Report, and Summarize
Make intelligent choices
See through the marketing hype
Key to understanding underlying organizational
motivation
Why is some hardware better than others for
CSE220 Lecture 21
MIPS Multicycle Datapath New Instructions
Modifications to the Multicycle datapath must be considered in stages.
Any new instructions should be broken into subtasks/sub-stages which
CSE220 Lec 8 & 9
MIPS Instruction Set Architecture & Datapath
We have studied various building blocks, such as the register file and the ALU.
Next we will examine how to connect these building blocks
MIPS
Microprocessor without Interlocked Pipeline Stages
Designed in early 1980s by John Hennessy
(SB Alum, now president of Stanford University).
Register machine (32 registers)
RISC architecture
CSE220 Lecture 20
Sequential Circuits & MIPS Multicycle Datapath Control
Mainly up until this point, we have discussed logic gates in combinatorial circuits. Combinatorial circuits
take stable input v
CSE220 Lecture 22
MIPS Recursive Programming Examples
(Text originally from Charles Lin at UMD corrections made)
An Example
Let's solve the following recursive function, written in C. This sums all el
Lecture 15
Branching, & Control Structures in MIPS
Branch instructions allow for the changing of the flow of the program. Without them, the program will
continue in a straight line of execution.
Two t
Von Neumann Architecture
The term von Neumann architecture refers to a particular design
model for a stored-program digital computer.
Separate central processing unit (CPU) and random-access
memory (
Converting Decimal Fractions to Binary
To obtain the binary digits corresponding to a decimal value less
than 1:
Generate bits left-to-right, starting at radix point:
Multiply the decimal value by 2
CSE220 Lecture 16
Function and Procedure Calls in MIPS
Functions allow for more structured programs, code reuse, and makes code easier to understand and
maintain.
Function Call Steps
There are 6 steps
CSE220 Lecture 10
Basic MIPS Datapath Adding Instructions
The basic datapath we have built only implements the instructions lw, sw, beq, R-type and jump. In order to
add the other instructions from th
CSE320 Lecture 6
Adders & Arithmetic Logic Unit (ALU)
A major component of a processor.
Arithmetic part does addition and subtraction of two numbers.
Logical part calculates bitwise AND & OR of two va
CSE220 Lecture 5
Demultiplexors, Decoders, Encoders, Adders
Demultiplexor
Inverse of a multiplexor.
It connects or routes its single input to one of 2n outputs depending on the value of the selector/c
CSE220 Lecture 4
Building Components & Multiplexors
Building Components
Boolean Logic is the tool to build any hardware unit with a defined functionality.
Example 1:
Lets design a black box with a d
Lecture 3
Digital Logic: Karnough Maps
Karnaugh Maps
Karnaugh maps, k-maps for short, are a graphical way to minimize Boolean functions.
So what is a Karnaugh map?
A Karnaugh map provides a pictoria
CSE220 Lecture 2
Combinatorial Digital Logic (contd)
Boolean Identities
o The key to simplifying Boolean expressions is to learn the Identities.
Double Complement:
(A')' = A
Idempotence:
AA = A
A+A
CSE320 Lecture 1
Combinatorial Digital Logic
Digital Logic is how all instructions and calculations are implemented.
o Underlying representation of storage, memory, calculations, etc.
o Study to under
Binary Digits
All data is ultimately represented in a computer in terms of bits
(binary digits).
Each bit is either a 0 or a 1.
Groups of bits represent higher-level values.
1101 1110 1010 1101 1011