ECEN 5007: Problem F2
1/1
Design a Schmitt trigger to meet the following specifications:
Trip point for rising inputs: VTRP + = 3.5V
Trip point for falling inputs: VTRP = 2.5V
Maximum propagation delay (rising or falling): t p 50ns
With the following d

ECEN 5007:
1/1
Clock generator design: Design an on-chip clock generator to meet the following specifications:
Clock frequency: 500 kHz (nominal)
Duty cycle: 50 %
Cell I/O: No inputs, only one output: clock
o Top cell symbol view should be a block with

ECEN 5837: Charge scaling DAC
1/1
3-Bit Charge Scaling DAC
Design a 3-bit charge scaling DAC based on the serial charge redistribution approach (e.g.
using two capacitors, three switches and digital control logic). Meet the following
specifications:
Maxi

ECEN 5837: Homework #3
1/1
Differential comparator:
Design a 2-stage, open-loop, SR limited comparator (differential in, single-ended out) to
meet the following specifications:
Total propagation delay (rising or falling): t p 100ns with 1pF load capacita

ECEN 4228: Problem G.3
1/2
Op-amps used in the SC integrators in this problem can be considered ideal, except that the output
voltage cannot exceed the supplies: VOmax = VDD = +5V, and VOmin = ,VSS = ,5V.
(a) Sketch an inverting, parasitic-insensitive SC

ECEN 5837: SAR ADC
1/1
3-Bit SAR ADC
Design a 3-bit successive approximation ADC. Meet the following specifications:
Operation up to 1 MSPS (mega-sample-per-second)
I/O:
o Dout: 3-bit parallel latched digital output
o Vin: input voltage, 1V peak-to-peak

ECEN 4228: Problem G.1
1/2
In this problem the op-amps can be considered ideal except that the op-amp output voltage cannot exceed
the limits equal to the supply voltages, Vomax = VDD = 5V, Vomin = ,VSS = ,5V. Switches have very
small on-resistances Ron .

ECEN 4228: Problem G.4
1/2
Figure below shows a collection of switched-capacitor circuits. In all cases, assume that the switches
have very low on resistance Ron , and that the op-amps are ideal except that the op-amp output voltage
cannot exceed the limi

ECEN 4228: Problem G.2
1/1
Figure below shows a 2nd -order continuous-time bandpass lter. You can assume that all op-amps have
ideal characteristics.
R3
R
C
C
R
R
R2
+
vo
R
+
+
vi
(a) Find the transfer function H s = vo =vi of the lter and put it in the f

ECEN 5007: Problem G5
1/1
SC Analysis
The figure below shows an SC circuit driven by two non-overlapping clocks, 1 & 2.
Assume that tThe sampling instants t = nTs are at the rising edge of 1, and that the
following capacitors are matched:
C 2 = C3 = C 4 =

ECEN 5007: Problem H3
1/1
Complete 4-Bit ADC Design and Verification: Design a complete 4-bit 1 MSPS (mega-sample-persecond) successive approximation ADC given the following constraints and suggested design steps.
Design Constraints:
Your final design sh

ECEN 5007: Problem F1
1/1
Design a 2-stage, open-loop, SR limited comparator (differential in, single-ended out) to
meet the following specifications:
Total propagation delay (rising or falling): t p 60ns
Input common-mode range, ICMR: 0.5V VIC 3.5V
Outp

ECEN 5007: Problem E1
1/1
Design a fully differential version of the symmetrical CMOS OTA with CMFB based on the
two differential amp approach to sensing the common-mode output and feeding back the
bias current. The design should meet the following specif

ECEN 5007: Problem F3
1/1
Latched Comparator Analysis
For the latched (clocked) comparator comp_latch given in the ecen5007ref library on
magellan, the objective in adding the latching transistor (M24) was to allow the outputs to
swing rail-to-rail.
As th

ECEN 5837: Latched comparator with hysteresis
1/1
Latched differential comparator with hysteresis:
Design a latched comparator with hysteresis to meet the following specifications and perform
the testing and additional design as described below.
Valid op

ECEN 5007: Problem H1
1/1
4-Bit DAC Design & Simulation
Design a simple 4-bit DAC based on binary weighted current mirrors and differential switch
cells by performing the following steps.
1. Perform the design in the AMS 0.35u process (c35b4). Follow the

ECEN 5007: Problem H2
1/1
4-Bit ADC Design & Simulation
Design a 4-bit successive approximation ADC based on your DAC from Problem H1 by
performing the following steps.
1. Again, design in the AMS 0.35u process (c35b4).
2. Design a successive approximatio

ECEN 5007 Mixed-Signal IC Design
Spring 2005
HW #2: Fully Differential Amplifier Design
DUE: Tuesday, February 1, 2005
1. Design, simulate, layout and verify a fully differential amplifier with CMFB to meet the following
specifications:
Low frequency dif

ECEN 5007: Problem F4
1/1
Oscillator Design (comparators with hysteresis)
Design an on-chip oscillator using a comparator with internal hysteresis to meet the
following specifications:
Nominal output frequency: 500 kHz
Load capacitance: 10 pF
Your desig

ECEN 5837: Current steering DAC
1/1
3-Bit Current Steering DAC
Design a 3-bit DAC based on identical current mirrors (thermometer code) and differential
switch cells based on the following specifications.
Maximum conversion time: Tc_max = 100 ns
Output

ECEN 5007: Problem G2b SC Filter Design in Cadence
1/1
Perform the following based on your results from Archive, Problem G2:
1. Solve for the Z-transform of your 2nd-order filter from G2 part (b) using a signal flow graph approach.
2. Find a suitable solu