In-Class Exercise 21 Solution
Class 21: 3 March 2014
Reverse Engineering
Figure 1: Finite-state machine implementation with D flip-flops and multiplexers
Sometimes we must reverse engineer an implementation to its specification. For finite-state machines,
In-Class Exercise 5 Solutions
Class 5: 24 January 2014
Problem Description
Consider the patient monitoring system shown above. Your task is to design and implement the control
logic for a patient monitoring system. The monitoring system has the following
In-Class Exercise 13 Solution
Class 13: 12 February 2014
SR Latch
Consider the timing diagram showing the values of control inputs S and R. Finish the timing diagram
by showing the waveforms for outputs t and Q.
Illustration 1:
In-Class Exercise 15 Solution
Class 15: 17 February 2014
Problem Description
Consider the finite-state machine diagram shown below. The output Out is 0 for states A and B, and is
1 for state C. Assume that the rising edge of the clock is the active clock
In-Class Exercise 22 Solution
Class 22: 5 March 2014
Shift Register Design (Data and Control Paths)
Design a 4-bit shift register with the following behavioral specification.
Shift Function Select
F1(t)
F0(t)
Output
0
0
Hold Current Value
0
1
Shift Left b
In-Class Exercise 6 Solutions
Class 6: 27 January 2014
1 Problem Description
Prove DeMorgan's Law (hint: use a truth table)
(a) (a + b)' = a'*b'
(b) (a*b)' = a' + b'
a
b
(a + b)'
a'*b'
(a*b)'
a' + b'
0
0
1
1
1
1
0
1
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
0
Table 1
In-Class Exercise 19 Solution
Class 19: 26 February 2014
Design Task
Design a 4-bit multifunction register with the following behavior:
s1
s0
Operation
0
0
Maintain present value
0
1
Parallel load
1
0
Shift right
1
1
Reset to 0
Table 1: Specification of M
In-Class Exercise 4 Solutions
Class 4: 22 January 2014
Problem Description
Consider the schematics shown below. Fill in the tables below assuming logic 1 = 3 volts and logic 0 =
0 volts.
In-Class Exercise 8 Solutions
Class 8: 31 January 2014
Design a 1-bit Adder
You are to design a circuit that adds two one-digit binary numbers and
binary number
corresponding to the sum of and . For example, if
base-10 sum of and is
which is
.
and produce
In-Class Exercise 11 Solution
Class 11: 7 February 2014
Implementation of a 2:4 Decoder with an Enable
Recall the definition of a 2-4 decoder with an enable, which is shown below.
Recall the definition of a 1-2 decoder with an enable, which is shown below
In-Class Exercise 17 Solution
Class 17: 21 February 2014
Use Case Description
Our job is to design a finite-state machine (FSM) to satisfy the following use case. We want to count
the number of people passing through a narrow corridor that only allows one
In-Class Exercise 18 Solution
Class 18: 24 February 2014
1 Design Task: Memory with Load Control
Your task is to implement the following specification with a D-flip flop and a 2:1 multiplexer. Fill in
the timing diagram for the values shown and draw your
In-Class Exercise 14 Solution
Class 14: 14 February 2014
1 Data Latch
Consider the data latch shown below. Give a tabular description of its behavior. (Hint: recall how the
table for a SR latch works and think about the effects of the two AND gates and IN
In-Class Exercise 10 Solutions
Class 10: 5 February 2014
1 Implementation of a 4:1 Multiplexer
Figure 1.1: Tabular Specification of 4:1 Multiplexer
Consider the tabular specification of a 4:1 multiplexer shown in Figure 1.1. Write the formula
correspondin
In-Class Exercise 7 Solutions
Class 7: 29 January 2014
Problem Description
Canonical forms (standard representations), such as sum-of-minterms representation, are a compact
form for specifying truth tables and logical formulas. They are an unambiguous in
In-Class Exercise 9 Solutions
Class 9: 3 February 2014
1 Shannon's Expansion
Consider the following combinational logic formula with three inputs.
(a) Using the above definition of
(b) Rewrite
, calculate the following values
into an equivalent form using
In-Class Exercise 16 Solution
Class 16: 19 February 2014
Problem Description
Consider the finite-state machine diagram shown below. The output Out is 0 for states A and B, and is
1 for state C. Assume that the rising edge of the clock is the active clock
In-Class Exercise
Class 2: 15 January 2014
1 Design Description
Consider the block diagram of the system shown below consisting of an analog-to-digital converter, a
digital processing unit, and a digital-to-analog converter.
Figure 1.1: System Block Diagr
In-Class Exercise Solutions
Class 2: 15 January 2014
1 Design Description
Consider the block diagram of the system shown below consisting of an analog-to-digital converter, a
digital processing unit, and a digital-to-analog converter.
Figure 1.1: System B
CSE261
Spring 2008
Positional Number System
Number Systems And Codes
Positional Positional Binary
General form of a number:
Most significant digit (MSB)
Least significant digit (LSB)
number systems number system conversions
dp-1dp-2..d0.d-1d-2
CSE261
Spring 2008
Encoders vs. Decoders
1. 2. 3. 4.
Encoders Three-state Outputs ThreeMultiplexers XOR gates
Decoder
Encoder
Inverse function of a Decoder. Outputs are less than inputs.
output code input code ENCODER
Converts input code word
CSE 261
Spring 2008
A Generic Digital Processor
Building Blocks for Digital Architectures
RAM, ROM, Buffers, Shift registers
Bit-Sliced Design BitControl
INPUT - OUTPUT
MEMORY
CPU
Bit 3
Multiplexer
Register
Shifter
Adder
CONTROL DATAPATH
F