Final Pretest exercises 112515
These are some pretest exercises that will help you prepare for
the Final. They may be similar to some questions on the final
but there will be questions drawn directly from the lectures,
quizzes, midterm, homework, and labs
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CSE/EEE120 Fall 2012 Midterm
Name:
ASU ID:
You have 75 minutes to complete and turn in this quiz. Each question is worth 10 points. Please
read questions carefully and provide the answers in the form requested. SHOW YOUR WORK.
Good luck!
1. Given the foll
Prologue
The exercises contained in the simulation portion of this digital-design course are meant to lead you step-by-step
through the construction of an elementary microprocessor. At this point in your digital-design course, this may
seem like an immens
Simulation Lab 4: The Microprocessor
Prerequisites: Before beginning this laboratory experiment you must be able to:
Use Logisim.
Have completed Simulation Lab 1: Half Adder, Increment & Two's Complement Circuit.
Have completed Simulation Lab 2: 4-Bit Ful
1.0 Introduction
In this lab, I constructed a vending machine controller circuit based upon a given and assumed design specification. The objective of the lab was to gain experience using mediumscale-integrated circuit to build a controller and to gain th
CSE/EEE 120
Simulation Lab 1 Answer Sheet
Half Adder, Increment & Twos Complement Circuit
Name:_
Date:_
Task 1-1: Build and Test the 1-Bit Half-Adder
Include a picture of your Logisim circuit implementation of a 1-bit half adder here:
Follow the testing p
CSE/EEE120 Fall 2012
Group Quiz (Quiz #2)
Names:
You have 20 minutes to complete and turn in this quiz. Each question is worth 20 points. Please
read questions carefully and provide the answers in the form requested. SHOW YOUR WORK.
Good luck!
1. Answer t
Be sure to attach your Lab Data Sheets!
YOU MUST OBTAIN A STAMP AND SIGNATURE ON YOUR LAB
DATASHEET (OR DATA SHEET SUBSTITUTE FORM) AT THE FRONT
DESK IN GWC-273 LAB BEFORE LEAVING THE HARDWARE LAB
EEE/CSE 120
Hardware Lab 2 Answer Sheet
TTL Characteristic
Introduction In this lab, the expected learning objective of this lab is to gain experience using LogicWorks to build and debug circuits and subcircuits that perform mathematical operations and route data. After the completion of the lab, I will be able t
CSE/EEE120 Fall 2012
Individual Quiz (Quiz 1)
ASU ID:
Name:
You have 30 minutes to complete and turn in this quiz. Each question is worth 20 points. Please
read questions carefully and provide the answers in the form requested. SHOW YOUR WORK.
Good luck!
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CSE/EEE 120
Simulation Lab 2 Answer Sheet
4-Bit Full Adder, Multiplexer, Decoder & Buffer
Name:_
Date:_
Task 2-1: Design a Full Adder
Write down the canonical SOP expressions for the Cout and SUM function of a full adder. Be sure to check
the lab manual f
CSE/EEE120 Fall 2012 Midterm
Name:
ASU ID:
You have 75 minutes to complete and turn in this quiz. Each question is worth 10 points. Please
read questions carefully and provide the answers in the form requested. SHOW YOUR WORK.
Good luck!
1. Given the foll
Introduction In this lab, the expected learning objectives were to gain experience in building and using latches, flip-flops, and registers and using these skills to lead into building a 2-bit binary up counter. After the completion of the lab, I will und
1.0 Introduction
In this lab, I constructed a brainless microprocessor in LogicWorks. I completed the design with three different types of memory and various communications busses. A human could carry out simple operations by controlling the processor. Af
Be sure to attach your Lab Data Sheets!
YOU MUST OBTAIN A STAMP AND SIGNATURE ON YOUR LAB
DATASHEET (OR DATA SHEET SUBSTITUTE FORM) AT THE FRONT
DESK IN GWC-273 LAB BEFORE LEAVING THE HARDWARE LAB
EEE/CSE 120
Hardware Lab 1 Answer Sheet
Debugging a Half a
CSE/EEE 120 Spring 2016
Individual Quiz (Quiz 1)
Name: A‘KﬁWV ASUID:
You have 30 minutes to complete and turn in this quiz. Please read questions carefully and provide the
answers in the form requested. SHOW YOUR WORK. You can use one 8 1/2 by 11inch shee
Introduction In this lab, the expected learning objectives were to understand the results of improper wiring practices and the functionality and wiring of a three-state and open-collection buffer. After the completion of the lab, I will understand how to
Introduction In this lab, the expected learning objectives were to understand how to use TTL ICs to build and debug logic circuits and understand how to use the exclusive OR operator with both the sum-ofproduct and product-of-sum forms. After the completi
Introduction In this lab, the expected learning objective of this lab is to gain experience using pre-created circuits from previous labs to create a fully functions arithmetic and logic unit. After completing this lab, I will be able to build, test, debu
ward)
On the basis of your measurements can you conclude that the total resistance R: of two resistors R1
and R2 connected in series is given by the equation: R1= R1 + R2?
Hint: V1 = V] + V2 0 DR; =11'R1 + Iz'Rz.
Measure the effective resistance R using t
S. Chickamenahalli
CSE 120 Spring 2017
HW1
Max points 100
Problem 1: (2 + 2 + 2 + 2 + 2 pts) Show a truth table for each of the following circuits:
a)
A
B
b)
A
B
Y
Y
c)
A
B
C
Y
d)
A
B
C
Y
e)
A
B
C
Y
Problem 2: (14 pts) Determine, using a truth table, whet
PHY 132
Capacitor
Name: Zihao Feng
Partner: Jacob Smith
Section: 10511 Group #: 3
TA: Malkiyat Singh
13/2/2017
Abstract:
This lab measures and calculate the voltage in a circuit, and to prove the
conservation of charge principle.
In part #1 1d), the expec