Hardware Design Languages and hardware Programming
ECE 333

Spring 2008
EEE333
HW#4
Charles Wong
1.
Data Path with Parity Check Design a data path and a controller to repeatedly receive characters in 7bit odd parity format (ie., the parity bit is 1 if the number of ones in a given set of bits is even). The bits are r
Hardware Design Languages and hardware Programming
ECE 333

Spring 2008
Charles Wong Lab #2 Arithmetic Logic Unit EEE 333
Professor Yu (Kevin) Cao March 5, 2008
Objective The objective of lab exercise #2 is to practice our VHDL coding and the modeling of combinational logic units. We were to model an 8bit Arithmetic /
Hardware Design Languages and hardware Programming
ECE 333

Spring 2008
EEE 333, ASU Spring 2008, Yu (Kevin) Cao Homework #4 Due Thursday, April 3rd, 10am, submitted to me in class. The objective of homework 04 is to practice advanced coding skills. You may use modelsim to check your answers. Data Path with Parity Check
Hardware Design Languages and hardware Programming
ECE 333

Spring 2008
EEE 333, ASU Spring 2008, Yu (Kevin) Cao Homework #4 Data Path with Parity Check
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity parity is generic ( length : integer := 7); port ( clk :
Hardware Design Languages and hardware Programming
ECE 333

Spring 2008
EEE 333, ASU Spring 2008, Yu (Kevin) Cao Homework #5 Parity Tree Design
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity xor_out is generic ( length : integer := 8); port( rx : in std_lo
Hardware Design Languages and hardware Programming
ECE 333

Spring 2008
EEE 333, ASU Spring 2008, Yu (Kevin) Cao Lab #5 Due Friday, April 25th. The objective of this lab is to practice your FPGA design knowledge. Submission: Submit a file with the VHDL code to the digital drop box. You must demonstrate your work to the T
Hardware Design Languages and hardware Programming
ECE 333

Spring 2008
EEE333 HW#2 Chapter 2. Exercises 1, 6, 7, 8 Chapter 4. Exercise 4. Chapter 5. Exercise 3, 4
Charles Wong
1. Write constant declarations for the number of bits in a 32bit word and for the number (3.14159).
6.
Given the type declaration type stat
Hardware Design Languages and hardware Programming
ECE 333

Spring 2008
EEE 333, ASU Spring 2008, Yu (Kevin) Cao Homework #1 Due Tuesday, February 5th, 10am, submitted to me in class. The objective of this homework is to practice your knowledge of combinational and sequential logic, as well as the implementation with CMO
Hardware Design Languages and hardware Programming
ECE 333

Spring 2008
EEE 333, ASU Spring 2008, Yu (Kevin) Cao Homework #3 Due Tuesday, March 18th, 10am, submitted to me in class. The objective of homework 03 is to practice the VHDL coding of finite state machines. Please review related lectures and book chapters to st
Hardware Design Languages and hardware Programming
ECE 333

Spring 2008
EEE 333, ASU Spring 2008, Yu (Kevin) Cao Lab #1 No due date. You dont need to turn in anything. The objective of this lab is to help you be familiar with the simulation environment, which is important for other labs during this semester. Tutorial (/u
Hardware Design Languages and hardware Programming
ECE 333

Spring 2008
Charles Wong Lab #3 12bit SRAM with 128 Address Locations EEE 333
Professor Yu (Kevin) Cao April 1, 2008
Objective The objective of lab exercise #3 is to practice our VHDL coding and the modeling of memory design and test schemes. We were to model
Hardware Design Languages and hardware Programming
ECE 333

Spring 2008
EEE 333, ASU Spring 2008, Yu (Kevin) Cao Lab #2 Due Thursday, March 6th. The objective of this lab is to practice your VHDL coding and the modeling of combinational logic units. Submission: Demo your results to the TA at least one day before the dead
Hardware Design Languages and hardware Programming
ECE 333

Spring 2008
EEE 333, ASU Spring 2008, Yu (Kevin) Cao Lab #4 Due Thursday, April 11st. The objective of this lab is to be familiar with on the Spartan3 FPGA board. Submission: Submit a file with the VHDL code to the digital drop box. You must demonstrate your wo
Hardware Design Languages and hardware Programming
ECE 333

Spring 2008
EEE 333, ASU Spring 2008, Yu (Kevin) Cao Lab #3 Due Tuesday, April 1st. The objective of this lab is to practice your VHDL coding, memory design, and test schemes. Submission: Demo your results to the TA at least one day before the deadline. Then pla
Hardware Design Languages and hardware Programming
ECE 333

Spring 2008
EEE 333, ASU Spring 2008, Yu (Kevin) Cao Homework #6 Due Thursday, April 24th, 10am, submitted to me in class. The objective of homework 06 is to practice the logic implementation with FPGA design. LookUp Table (LUT) The Xactix FPGA company decides
Hardware Design Languages and hardware Programming
ECE 333

Spring 2008
EEE 333, ASU Spring 2008, Yu (Kevin) Cao Homework #5 Due Tuesday, April 15th, 10am, submitted to me in class. The objective of homework 05 is to review advanced VHDL coding skills. Parity Tree Design Write the VHDL code to implement the following two
Hardware Design Languages and hardware Programming
ECE 333

Spring 2008
EEE333
HW#3
Charles Wong
1. VHDL Implementation Write the VHDL codes to implement the following Moore type FSM:
 Assignment: HW #3 (Moore State Machine)  Name: Charles Wong  File: HW#3.vhd library IEEE; use ieee.numeric_std.all; use ieee.nume
Hardware Design Languages and hardware Programming
ECE 333

Spring 2008
EEE 333, ASU Spring 2008, Yu (Kevin) Cao Homework #2 Due Thursday, February 14th, 10am, submitted to me in class. The objective of this homework is to exercise your learning of VHDL syntax, basic module definitions and modeling of combinational logic
Hardware Design Languages and hardware Programming
ECE 333

Spring 2008
EEE 333, ASU Spring 2008, Yu (Kevin) Cao Homework #3 1. VHDL Implementation
library IEEE use IEEE_Std_logic_1164.all; entity FSM is port( clk,reset F,IE2,IE3,PF Stall output end entity FSM; : : : : in std_logic; in std_logic; out std_logic; out std_l
Hardware Design Languages and hardware Programming
ECE 333

Spring 2008
Midterm II Review Highlights Sequential logic Finite State Machine Testbenches and effective coding skills Combinational vs. Sequential
s <= 1; if s = 1 then Delta delay lets us make realistic things like clock oscillators clk_gen: process is be