Q1. A logic circuit is given in Figure 1. For this technology, the minimum sized inverter has 3fF of
(a) Determine the delay from the input to X and Z assuming all gates are minimum sized.
(b) Size the gates to minim
Digital Systems and Circuits
Problem 1 (20 pts). A semiconductor company has the following costs associated with Product X:
Fixed cost of $500M ($500,000,000)
Die yield of 75% (75% of dies on a wafer make it to the next level)