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EE 108  Stanford Study Resources

Lect.9.Metastabilityblackschaffer
School: Stanford
EE108A Lecture 13: Metastability and Synchronization Failure (or When Good FlipFlops go Bad) 11/9/2005 EE 108A Lecture 13 (c) 2005 W. J. Dally 1 What happens when we violate setup and hold time constraints? d D Q q clk d clk q 11/9/2005 ts

EE108_hw2_sol
School: Stanford
Course: Digital Systems I
EE108A Fall 20132014 Homework 2 Solutions 1. Adders (15 points) AJ 10/6/13 1 EE108A Fall 20132014 s = (a & ~b & ~cin)  (~a & b & ~cin)  (~a & ~b & cin)  (a & b & cin 2. Multiplexor Fun (7 points) AJ 10/6/13 2 EE108A Fall 20132014 3. Gen

EE108_hw4_sol (1)
School: Stanford
Course: Digital Systems I
EE 108 Fall 20142015 Homework 4 Solutions 1. Homing Sequences (10 Points) No matter what state the FSM is in, if we pulse in high for one clock cycle and then wait a minimum of four more cycles holding in low, we can guarantee that our FSM will

EE108_hw3_sol
School: Stanford
Course: Digital Systems I
EE108A Winter 20132014 Homework 3 Solutions 1. Combinational Logic Design (10 pts) 2. Negative Integer Representation (8 pts) a. b. c. d. 17 is 0b0010001 17 is 0b1101111 31 is 0b1100001 32 is 0b1100000 3. Binary to Decimal FixedPoint Conversion (9 pt

EE108A.hw4.v2 (1)
School: Stanford
Course: Digital Systems I
EE108: Digital System Design Fall 20142015 Homework 4 Due Monday, October 20th at the beginning of class 1. Homing sequences (7 points)  The nitestate machine described by the table below does

EE108A.sol.hw1 (1)
School: Stanford
Course: Digital Systems I
Fall 2013 EE108A: Digital Systems Homework 1 Solutions Due Monday, October 7th at the beginning of class 1. Encoding (5 points) Assuming we need to find a good encoding to represent dates, what property should our encodi

EE108A_hw3
School: Stanford
Course: Digital Systems I
EE108: Digital Systems Fall 2014 Homework 3 Due Monday, October 13th at the beginning of class 1. Combinational Logic Design Design a circuit that accepts three 4bit numbers, a2[3:0], a1[3:0

EE108a+Section+1+Handout
School: Stanford
Course: Digital Systems I
EE108a Section 1 Handout Verilog cheat sheet Datatypes When to use wires and regs: A signal changed in an always block must be delcared as a reg. A signal changed in an assign statement must be declared as a

EE108a+Section+2+Handout
School: Stanford
Course: Digital Systems I
EE108a Section 2 Handout More Verilog Parameters Parameters can be declared in the module header: module module_name #( parameter name1 = default1, parameter name2 = default2, ) (

EE108a_Section_4_Handout
School: Stanford
Course: Digital Systems I
EE108a Section 4 Handout Sequential logic Stateful circuits A flipflop is a unit of memory. When designing sequential logic, figure out what signals your circuit needs to remember about the task its doing, and make a flipflop for each of them. Never conne

EE108ASection1Notes
School: Stanford
Course: Digital Systems I
EE108A Section #1 September 29, 2011 1) Noise Margins A logic family uses signal levels relative to VDD as shown in the following table: Parameter Value VOL 0.2VDD VIL 0.4VDD VIH 0.6VDD VOH 0.8VDD We connect two logic subsystems A and B using this logic f

EE108a+Section+3+Handout
School: Stanford
Course: Digital Systems I
EE108a Section 3 Handout Number representation Fixed point We can represent numbers that have fractional digits in binary the same way we do in decimal: 0 0 1 1 0 1 . 0 1 1 13.375 = ! ! ! 25=

EE108_hw2
School: Stanford
Course: Digital Systems I
EE108: Digital Systems Autumn 2014 Homework 2 Due Monday, October 6th at the beginning of class 1. Adders (15 points)  A half adder is a circuit which takes in 1bit binary numbers a and b

Lect61.v2
School: Stanford
Course: Digital Systems I
Lecture 6 Sequential Logic Examples & Timing Analysis Subhasish Mitra Stanford University subh@stanford.edu Copyright 2013 by Subhasish Mitra With Major Contributions from Bill Dally 1 Administrivia Readings Chapters 15, 16, 17 Sequential logic example

Ee108a Final Project
School: Stanford
EE108A Digital Systems I Final Project Winter 06 07 Final Project: Enhanced Music Synthesizer and Display Introduction The final project will provide you with a complete digital systems design experience. It encompasses all of the elements you h

Ee108A03f06
School: Stanford
EE108A 10/1/2007 EE108A Lecture 3: Combinational Building Blocks 10/1/2007 EE 108A Lecture 3 (c) 2007 W. J. Dally and D. BlackSchaffer 1 Announcements Bill is out of town this week. Read Chapter 10 before Wednesday's Lecture You should

Ee108A09f07
School: Stanford
10/24/2007 EE108A Lecture 10: Microcode 10/24/07 EE 108A Lecture 9 (c) 2006 W. J. Dally and D. BlackSchaffer 1 Announcements Problem set 3 due Lab 4 hints Do a good clean design Lab 5 and the final project will reuse most of this lab Youll

Lect11.Introduction.v2
School: Stanford
Course: Digital Systems I
Lecture 1 The Digital Abstraction Combinational Logic Representation Verilog Subhasish Mitra Stanford University subh@stanford.edu Copyright 2014 by Subhasish Mitra With Major Contributions from Bill Dally EE108A Lecture 1 1 Lecture Outline Course overvi

Lect05.Midterm1.Review
School: Stanford
Course: Digital Systems I
Lecture 5 Numbers and Arithmetic Subhasish Mitra Stanford University subh@stanford.edu Copyright 2013 by Subhasish Mitra With Major contributions from Bill Dally 1 Announcements Homework 1 is graded and will be returned in class. Homework 2 due today at

Lect052.v6
School: Stanford
Course: Digital Systems I
Lecture 5 Sequential Logic Subhasish Mitra Stanford University subh@stanford.edu Copyright 2014 by Subhasish Mitra With Major Contributions from Bill Dally 1 Reading Chapter 14 from Dally & Harting 2 Announcements Lab 2 Due Thursday @ 12:00 p.m. Submit o

Lect.08
School: Stanford
Course: Digital Systems I
Lecture 8 Asynchronous Circuits Subhasish Mitra Stanford University subh@stanford.edu Copyright 2014 by Subhasish Mitra With Contributions from Bill Dally & E.J. McCluskey 1 Announcements HW 5 is Out Lab 4 Due Thursday at 12:00 p.m. 2 Asynchronous seque

EE108_hw1 (1)
School: Stanford
Course: Digital Systems I
EE108: Digital Systems Autumn 2015 Homework 1 Due Monday, September 29th at the beginning of class 1. Encoding (5 points) Assuming we need to find a good encoding to represent dates, what p

Lect02_v7
School: Stanford
Course: Digital Systems I
Lecture 2 Combinational Logic Design Subhasish Mitra Stanford University subh@stanford.edu Copyright 2013 by Subhasish Mitra With Major Contributions from Bill Dally EE108 Lecture 2 1 Announcements Lab & Section Signup Open today! Signup on Coursework i

Lect07
School: Stanford
Course: Digital Systems I
Lecture 7 Design Example Subhasish Mitra Stanford University subh@stanford.edu Copyright 2014 by Subhasish Mitra With Major Contributions from Bill Dally 1 Announcements Debugging Verilog Code Your responsibility to debug your code, TAs may help Lab 3

Lect03_v5
School: Stanford
Course: Digital Systems I
Lecture 3 Combinational Building Blocks Subhasish Mitra Stanford University subh@stanford.edu Copyright 2014 by Subhasish Mitra With Major contributions from Bill Dally 1 Announcements HW 1 Due Now HW 2 is out Lab 0 is this Thursday You must be enrolled i

EE108_hw5_sol
School: Stanford
Course: Digital Systems I
EE 108 Autumn 20142015 Homework 5 Solutions 1. Hazards (15 points) 1 EE 108 Autumn 20142015 2 EE 108 Autumn 20142015 2. Timing Analysis (10 points) 3. Fundamental Mode Analys