EE108: Digital System Design
Fall 2014-2015
Homework 4
Due Monday, October 20th at the beginning of class
1. Homing sequences (7 points) - The nite-state machine described by the table below does
EE 108
Fall 2014-2015
Homework 4 Solutions
1. Homing Sequences (10 Points)
No matter what state the FSM is in, if we pulse in high for one clock cycle and
then wait a minimum of four more cycles holding in low, we can guarantee that
our FSM will
EE108: Digital Systems
Autumn 2015
Homework 1
Due Monday, September 29th at the beginning of class
1. Encoding (5 points) Assuming we need to find a good encoding to represent dates, what p
Fall 2013
EE108A: Digital Systems
Homework 1 Solutions
Due Monday, October 7th at the beginning of class
1. Encoding (5 points) Assuming we need to find a good encoding to represent dates, what property
should our encodi
Lecture 2
Combinational Logic Design
Subhasish Mitra
Stanford University
[email protected]
Copyright 2013 by Subhasish Mitra
With Major Contributions from Bill Dally
EE108 Lecture 2
1
Announcements
Lab & Section Signup Open today!
Signup on Coursework i
Lecture 6
Sequential Logic Examples & Timing Analysis
Subhasish Mitra
Stanford University
[email protected]
Copyright 2013 by Subhasish Mitra
With Major Contributions from Bill Dally
1
Administrivia
Readings
Chapters 15, 16, 17
Sequential logic example
EE108: Digital Systems
Autumn 2015-2016
Homework 1
Due Monday, Oct. 5th at the beginning of class
1. Encoding (5 points) Assuming we need to find a good encoding to represent dates, what
property should our encoding have so that it is easy to determine if
EE108 Digital System Design
Autumn 2015-16
Homework 4
Due Wednesday, 28 October, at the beginning of the class
1.
Timing (20 points)
EE108 Digital System Design
Autumn 2015-16
3. More Timing (20 points)
a. The above circuit is violating a timing constrain
EE108: Digital Systems
Autumn 2015-2016
Homework 2
Due Friday, Oct. 9th by noon in Packard 128
1. Adders (15 points) - A half adder is a circuit which takes in 1-bit binary numbers a and b and
outputs a sum s and a carry out co. The concatenation of co an
EE108: Digital Systems
Autumn 2015-2016
Homework 3
Due Wednesday, Oct. 21st at the start of class
1. Homing Sequences (7 points) The finite-state machine described by the table belwo does
not have a reset input. Explain how you can get the machine in a kn
EE108 Lab 3
Bike Light FSM
Lab Due: 10/21/15
Objective: The purpose of lab 3 is to introduce you to the construction of finite state machines
and sequential logic design in Verilog.
1. Introduction
A Warning
This lab is significantly more involved than an
EE108 Lab 2
Floating Point Adder
Lab Due: 10/14/2015
Objective: The purpose of lab 2 is to introduce you to floating point arithmetic and give you a chance to
structure a complex Verilog module from scratch
1. Introduction
So, what are we doing here?
This
EE108 Lab 1
Password Hashing
Lab Due: 10/7/15
Objective: The purpose of lab 1 is to give you experience designing combinational logic and writing a
wide variety of Verilog constructs.
1. Introduction
So, what are we doing here?
In this lab we'll be design
EE108 Lab 0
Introduction to Verilog and the EE108 Toolchain
Due: Read before your assigned lab session, complete sections 3, 4, and 5 during your lab session.
Objective: The purpose of lab 0 is to familiarize you with the concepts and tools we will be usi
Lecture 8
Timing Analysis
Subhasish Mitra
Stanford University
[email protected]
Copyright 2016 by Subhasish Mitra
With Major Contributions from Bill Dally
1
Administrivia
Readings
Chapters 15, 16, 17 (continue timing analysis for Thursday)
Announcement
EE108: Digital Systems
Winter 2015-2016
Homework 3
Due Tuesday, Feb. 2nd at the start of class
1. Homing Sequences (7 points) The finite-state machine described by the table belwo does
not have a reset input. Explain how you can get the machine in a known
EE108a Section 3 Handout Number representation
Fixed point
We can represent numbers that have fractional digits in binary the same way we do in decimal:
0
0
1
1
0
1
.
0
1
1
13.375 =
!
!
!
25=
EE108A Section #1
September 29, 2011
1) Noise Margins
A logic family uses signal levels relative to VDD as shown in the following table:
Parameter
Value
VOL
0.2VDD
VIL
0.4VDD
VIH
0.6VDD
VOH
0.8VDD
We connect two logic subsystems A and B using this logic f
EE108a Section 4 Handout Sequential logic
Stateful circuits
A flipflop is a unit of memory. When designing sequential logic, figure out what signals your
circuit needs to remember about the task its doing, and make a flipflop for each of them.
Never conne
EE108 Lab 5
Waveform Display
Lab Due: 11/4/15
Objective: The purpose of lab 5 is to render the waveform being outputted by lab 4 to a raster
display.
1. Introduction
So, what are we doing here?
In lab 5, you will use the audio samples generated in lab 4 t
Chapter 14
Sequential Logic
The output of sequential logic depends not only on its input, but also on its state
which may reflect the history of the input. We form a sequential logic circuit via
feedback - feeding state variables computed by a block of co
1
Analog and Digital Signals,
Time and Frequency
Representation of Signals
Required reading:
Garcia 3.1, 3.2
CSE 3213, Fall 2010
Instructor: N. Vlajic
2
Data vs. Signal
Analog vs. Digital
Analog Signals
Simple Analog Signals
Composite Analog Signals
Lecture 1
The Digital Abstraction
Combinational Logic Representation
Verilog
Subhasish Mitra
Stanford University
[email protected]
Copyright 2014 by Subhasish Mitra
With Major Contributions from Bill Dally
EE108A Lecture 1
1
Lecture Outline
Course overvi
Lecture 5
Sequential Logic
Subhasish Mitra
Stanford University
[email protected]
Copyright 2014 by Subhasish Mitra
With Major Contributions from Bill Dally
1
Reading
Chapter 14 from Dally & Harting
2
Announcements
Lab 2 Due Thursday @ 12:00 p.m.
Submit o
Lecture 8
Asynchronous Circuits
Subhasish Mitra
Stanford University
[email protected]
Copyright 2014 by Subhasish Mitra
With Contributions from Bill Dally & E.J. McCluskey
1
Announcements
HW 5 is Out
Lab 4 Due Thursday at 12:00 p.m.
2
Asynchronous seque
Lecture 7
Design Example
Subhasish Mitra
Stanford University
[email protected]
Copyright 2014 by Subhasish Mitra
With Major Contributions from Bill Dally
1
Announcements
Debugging Verilog Code
Your responsibility to debug your code, TAs may help
Lab 3
Lecture 3
Combinational Building Blocks
Subhasish Mitra
Stanford University
[email protected]
Copyright 2014 by Subhasish Mitra
With Major contributions from Bill Dally
1
Announcements
HW 1 Due Now
HW 2 is out
Lab 0 is this Thursday
You must be enrolled i
Lecture 6
Sequential Logic Examples & Timing Analysis
Subhasish Mitra
Stanford University
[email protected]
Copyright 2013 by Subhasish Mitra
With Major Contributions from Bill Dally
1
Administrivia
Readings
Chapters 15, 16, 17
Sequential logic example
EE108: Digital Systems
Autumn 2014
Homework 2
Due Monday, October 6th at the beginning of class
1. Adders (15 points) - A half adder is a circuit which takes in 1-bit binary numbers a and b