First, bring up the ModelSim program by double-clicking on the icon. This brings up the
ModelSim application, as shown below:
You will want to begin by creating a project that will hold your design. You can do this
by clicking File->New-
VHDL code for D flip flop
Note that code for combinational NAND, OR, XOR, and INVS gate is not provided because they
are straight forward.
Simulation for D Flip Flop
Code for D Flip Flop with enable and
Case statements code
Case statements simulation
Code for if-then-else
Simulation for if-then-else
When else code
When else simulation
Part 1. VHDL description for a 4 bit register with a load and clear.
Part 2. VHDL description for a counter with reset and increments.
Part 3. VHDL description for FSM that clears the register and resets the counter. In
Digital Systems Design Lab
1.A datapath is the collection of functional units, the brains of the system. It basically conducts the
flow of traffic in the system, defining routes that data can take.
North Carolina Agricultural & Technical State University
Department of Electrical and Computer Engineering
ECEN 429.11 Introduction to Digital System Laboratory
Laboratory No. 4
Instructor: C. Doss
Lab 2 was more extensive than last week's lab. For this lab it was broken up into 3 parts.
For the first portion of the lab, we were to simulate the VHDL code for a BCD-to-7 segment display
circuit. For the second portion of the lab we were t
State diagram for vending machine FSM.
Simulation for vending machine FSM
Input stands for dimes,nickle,gum,candy so if input is at 1 then that item has been selected.
If input is 1000 then it means a dime was e
North Carolina A&T State University
College of Engineering
Electrical and Computer Engineering Department
ELEN-423.01: Introduction to Digital Systems
Required Course _X_
Catalog Description: This course exposes the students to
entity ALU is
port(Sel: in std_logic_vector(2 downto 0);
A, B: in std_logic_vector(4 downto 0);
Output: out std_logic_vector(4 downto