ECE 464/520
Homework 0
The purpose of this REQUIRED homework and associated Moodle quiz is to evaluate
your preparation for this course. If you feel you need to review material to do this
homework, there are several good basic digital logic texts in the l
Digital ASIC Design
1. Introduction to ASIC Design
Dr. Paul D. Franzon
Genreal Outline
1. The wonderful world of Silicon
2. Application Specific Integrated Circuits (ASICs)
Typical applications, types, decision making
3. ASIC Design Flow
4. Trends
2015 Dr
ECE 464 / ECE 520
Homework 5
On-line turn-in. Turn in a brief report AND the Verilog file for your design (not your test
fixture or synopsys files) using wolfware. These will be checked using Code Comparison
tools. If your code is substantially similar to
ECE 464 / ECE 520
Homework 4
Hand in your solution, using the template at the end of this file as the first page of your
solution. You can edit this page but it must be turned in as a single cover sheet.
Question 1
The purpose of this question is to give
Digital ASIC Design
FPGA Design
Dr. Paul D. Franzon
Outline
1. Architectural Features of FPGAs
2. Design techniques specific to FPGAs
References
1. Xilinx Virtex5 documentation
2. S. Kilts, Advanced FPGA Design
2013 Dr. Paul D. Franzon, www.ece.ncsu.edu/
Digital ASIC Design
Low Power Design
Dr. Paul D. Franzon
Outline
1. Power consumption in CMOS
2. Strategies to reduce power consumption
3. Strategies to reduce energy/operation
References
Smith and Franzon, Chapter 11
Weste and Harris, Principles of CMO
Digital ASIC Design
Design For Test (DFT)
Dr. Paul D. Franzon
Outline
1. Motivation
2. Scan-based testing
3. Exhaustive testing, Memory testing, and BIST
4. DFT in Synopsys Environment
References
1. Kurup, Chapter 6.
2. M. Smith, Chapter 14.
2013 Dr. Pau
Digital ASIC Design
Finite State Machines
Dr. Paul D. Franzon
2013, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
1
Digital ASIC Design
Outline
Types of Finite State Machines
Coding Template
Controllers
Reset
References
1. Smith & Franzon,
Digital ASIC Design
3. Verilog I
Dr. Paul D. Franzon
Units within this module:
1. Introduction HDL-based Design with Verilog
2. A complete example: count.v
Design
3. A complete example: count.v
Verification Synthesis
4. Further examples
2013, Dr. Paul D.
ECE 520 Class Notes
Timing
Review Question:
What is the main goal of the global clock
distribution network?
A. Design the network so that the clock arrives
at each flip-flop at exactly the same time.
B. Design the network with deliberate skew to
give the
Digital ASIC Design
Verilog 1 Exercises
Review Question:
Convert the following into Verilog
always@(posedge clock)
begin
case (SumSelect)
2b00 : sum <= 4b0;
2b01 : sum <= sum + Data;
endcase
case (CheckError)
2b00 : error <= (sum = Data);
2b01 : error <=
Digital ASIC Design
4. Design With Verilog
Dr. Paul D. Franzon
Outline
1. Procedural Examples
2. Continuous Assignment
3. Structural Verilog
5. Common Problems
6. More sophisticated examples
Always Design Before Coding
2015, Dr. Paul D. Franzon, www.ece.n
Digital ASIC Design
4. Design With Verilog
Dr. Paul D. Franzon
Outline
1. Procedural Examples
2. Continuous Assignment
3. Structural Verilog
4. Common Problems
5. More sophisticated examples
Always Design Before Coding
2015, Dr. Paul D. Franzon, www.ece.n
Digital ASIC Design Class Notes
3. Verilog I
Dr. Paul D. Franzon
Major units within this module
1. Introduction HDL-based Design with Verilog
2. A complete example: count.v
Design
3. A complete example: count.v
Verification Synthesis
4. Further examples
2
Digital ASIC Design
3. Verilog I
Dr. Paul D. Franzon
Units within this module:
1. Introduction HDL-based Design with Verilog
2. A complete example: count.v
Design
3. A complete example: count.v
Verification Synthesis
4. Further examples
2013, Dr. Paul D.
Digital ASIC Design
Test Benches and Verification
Dr. Paul D. Franzon
Outline
1. Importance of Verification
2. Verilog Tools and Methods
Simulation
Non-synthesized models
Assertions
3. Metrics
4. Verification Environments and Random functional
5. Introduc
Digital ASIC Design
Designing a CPU
Dr. Paul D. Franzon
An example of a complex digital system
References
Patterson and Hennessey, Computer Organization and
Design, Ch. 4,5,6
Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
1
Digital ASIC Des
Digital ASIC Design
Techniques for Efficient Design
Dr. Paul D. Franzon
Outline
1. More on how to maximize Design Efficiency
References
1. Smith & Franzon, Chapter 10
2. H. Bhatnagar, Advanced ASIC Chip Synthesis Using Synopsys
Design Compiler, Physical C
Digital ASIC Design
3. Introduction to Design With Verilog
3.4 Exercises
Dr. Paul D. Franzon
2013, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
1
Digital ASIC Design
Exercise: Three Timing Examples (from Timing Notes)
What do these look li
Digital ASIC Design
3. Verilog I
Dr. Paul D. Franzon
Units within this module:
1. Introduction HDL-based Design with Verilog
2. A complete example: count.v
Design
3. A complete example: count.v
Verification Synthesis
4. Further examples
2013, Dr. Paul D.
Digital ASIC Design Class Notes
3. Verilog I
Dr. Paul D. Franzon
Major units within this module
1. Introduction HDL-based Design with Verilog
2. A complete example: count.v
Design
3. A complete example: count.v
Verification Synthesis
4. Further examples
2
Digital ASIC Design
3. Verilog I
Dr. Paul D. Franzon
Units within this module:
1. Introduction HDL-based Design with Verilog
2. A complete example: count.v
Design
3. A complete example: count.v
Verification Synthesis
4. Further examples
2013, Dr. Paul D.
Digital ASIC Design
2. Timing Design in Digital Systems
Dr. Paul D. Franzon
Outline
1. Timing design in Synchronous (clocked) Logic
Min/Max timing with flip-flops
Latch-based design
3. Timing Issues in CMOS circuits
4. Timing verification Flow
5. Techniqu
Digital ASIC Design
1. Introduction to ASIC Design
Dr. Paul D. Franzon
Genreal Outline
1. The wonderful world of Silicon
2. Application Specific Integrated Circuits (ASICs)
Typical applications, types, decision making
3. ASIC Design Flow
4. Trends
2013 Dr