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CSC-506: Architecture of Parallel Computers 1st Summer, 1999 Final Exam Question 1: (27 points 3 per step) A symmetrical multiprocessor computer system is
Memory-System Design A processor needs to retrieve instructions and data from memory, and store results into memory. We call this memory Random Access Memory (RAM).
There are two general types of Random Access Memo
Section 3.1 Principles of Pipeline Design Pipelining: Parallelism is achieved and performance is improved by starting to execute one instruction before the previous one is finished. The simplest kind of pipeline overlaps the execution of one instruction w
Vector Processors A vector processor is a pipelined processor with special instructions designed to keep the (floating point) execution unit pipeline(s) full. These special instructions are vector instructions. Terminology: Scalar a single quantity (numbe
Virtual Memory Systems
(with small cache) 2 - 5 ns
External Cache (Kbytes to Mbytes) 10 - 20 ns
Main Memory (Mbytes to Gbytes) 50 - 100 ns
Virtual Memory (Gbytes and up) 10 - 100 ms
Virtual memory is another level in the memory hierarchy. All g
CSC/ECE-506: Architecture of Parallel Computers 1st Summer, 1999 Mid-term Exam
Question 1: (25 points) A computer system has 16 megabytes of addressable memory and a 128 kbyte, 2-way set-associative cache with 16 bytes per line. The LRU replacement policy
Collision Analysis Assume we could implement on-chip cache and get the cache access time down to 1 clock, but implement it as a unified cache. Our new pipeline is:
Instruction Fetch - 5 ns
Instruction Decode - 5 ns
Address Generate - 5 ns
Operand Fetch -
Switch design for fast processor-to-memory transfer without contention.
Shared Memory 1 Shared Memory 2 Shared Memory 3
Shared Memory n
Architecture of Parallel Computers
Multiprocessor Systems A Multiprocessor system generally means that more than one instruction stream is being executed in parallel. However, Flynns SIMD machine classification, also called an array processor, is a multiprocessor but uses only a single ins
Architecture of Parallel Computers Architecture of high-performance computers This course is about high-performance computer architectures.
Usually, computer-systems architecture is differentiated from digital design, which is concerned with the details o
Memory System Homework due Monday, May 24, 1999.
1. A computer system uses 4-megabit memory chips and a 64-bit data bus. Draw a diagram and show the minimum number of memory chips we can use for each of the following chip configurations. What is the resul
Cache Homework due Wednesday, May 26, 1999
All problems from Stone chapter 2.
Problem 2.1, part a). Show the number of bits in each part of the address, the total cache size and a diagram of the cache organization.
Cache size = LKN = 64 x 4 x 256 = 64k by