Jaclyn Lim & Jameson Thomas Course: CSC 120 Section: 38356 Bruce Carlton Lab 1 Due: January 16th, 2010 Submitted: January 16th, 2010
The Objective(s)
1) The objective of Task 1 was to be able to turn
MUX_4
0 4 8 C 0 4 8 C 1 0 1 5 9 D 1 5 9 D 2 6 A E 2 6 A E 3 7 B F 3 7 B F A3 A2 A1 A0 B3 B2 B1 B0 A/B'
Y3 Y2 Y1 Y0
7
MUX_4
0 4 8 C 0 4 8 C 1 0 1 5 9 D 1 5 9 D 2 6 A E 2 6 A E 3 7 B F 3 7 B F A3 A2 A1
SEQUENCE.VHD library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all;
entity sequence is port( clk : in std_logic; reset : in std_logic; x: in std_logic; z : out std_logic; a : out std
S EQUENCE.VH D
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all;
entity sequence is port( clk : in std_logic; reset : in std_logic; x: in std_logic; z : out std_logic;
a : out s