Let's talk about INIT logic. The discussion will cover three topics: the rationale, the assumptions, and the implementation. The Rationale In much the same way that a flip-flop has an asynchronous input that takes the state of that flip-flop to some known
Problem 10.27 Find a two-level NOR implementation for a fundamental mode asynchronous sequential circuit with two inputs (x1, x2) and one output (z) that satisfies the following conditions: first, z is always zero when x2 = 1. The output z changes to logi
ECE ECE 3504 Digital Design I
Section 9: Iterative Design
Iterative? Iterative?
iterate (verb) to utter again or repeatedly. to do (something) over again or repeatedly. to operate or be applied repeatedly, as a linguistic rule as or mathematical formula.
ECE ECE 3504 Digital Design 1
Section 8: Circuit Prototyping using PROMs
Memory Memory Characteristics
In general, a memory module In having 2k addresses and m bits per address requires k address lines to choose one of the 2k addresses, th and m data lin
ECE ECE 3504 Digital Design 1
Section 7e: Glitches and Hazards
What What are Glitches?
We want to guarantee that an We output that shouldnt change as the result of a state transition doesnt change. We also want to guarantee that an output that should cha
ECE ECE 3504 Digital Design 1
Section 7d: State Assignment
Asynchronous Asynchronous Design Procedure Procedure
Parse the specification. Since there is no clock, the Mealy-Moore distinction doesnt apply. II. Model the system using a primitive flow table I
ECE ECE 3504 Digital Design 1
Section 7c: State Reduction
State State Reduction
Recall that the primitive flow table Recall is an incompletely-specified state table. As such, any approach that we take for reducing a primitive flow table will involve find
ECE ECE 3504 Digital Design 1
Section 7b: Modeling Asynchronous Sequential Circuits
Asynchronous Asynchronous Design Procedure Procedure
Parse the specification. Since there is no clock, the Mealy-Moore distinction doesnt apply. II. Model the system using
ECE ECE 3504 Digital Design 1
Section 7a: Introduction to Asynchronous Sequential Circuits
Synchronous Synchronous Circuits are Idealized are Idealized
So So far, we have considered clocked sequential circuits. Inputs change between clock pulses. All flip
For those of you with questions that you still havent asked: 1. What should the letters and numbers look like when they are shown on the display?
dot g dot g dot g dot g dot g dot g dot g dot g
a
a
a
a
a
a
a
a
Remember that youre using the part called 7-S
Problem 1 Design a 2-bit standard up counter. That is, a state machine that cycles through the states 00, 01, 10, 11. Design Process Generally speaking, the process of sequential design begins with the creation of a state diagram that describes the state
Problem 2 Design a dual-function counter. The counter has one control input, x, and a two-bit state. When x = 0, the counter should function as a standard-up counter, that is, it should cycle through the states 00, 01, 10, 11. When x = 1, the counter shou
Vignette: Proving Theorem 5 We want to prove that a + a ' b = a + b . Well show two different proofs. One will demonstrate the principle that sometimes Boolean algebra simplification requires steps that actually make an expression more complicated. The fa
When Karnaugh Maps Attack I use this function to motivate a demonstration of the Quine-McCluskey algorithm wherein a designer reaches the point where he cant choose any more prime implicants, either because none are essential or because none possess a qua
Deriving sum-of-products (SOP) and product-of-sums (POS) forms Every group you make on a Karnaugh map is a product term. When the product terms are unified, you've formed a sum-of-products expression. What makes the various SOP expressions different is if
Iterative Design: A Design Example
First, it is worth reviewing the points made in the document Iterative Design: A First Approach as to when it is appropriate or inappropriate to embark upon an iterative design for some system: Iterative design works whe
Iterative Design: A First Approach
Whether or not you know it, each of you has engaged in no fewer than two instances of iterative design during the course of taking ECE 2504. Of course, if everyone remembered and understood the design process in the spec
Another example of using dont cares to simplify logic equations: Suppose that we want to build a logic circuit that differentiates between multiples of 3 and non-multiples of 3. Additionally, suppose that we also know that all of the numbers will be input
Now that we have a counter, lets do something with it. Problem 3 Design the set of equations that will drive a seven-segment LED display to show the numeric equivalent of the value of the counters present state. Consider state A to be the bit of higher si
ECE ECE 3504 Digital Design 1
Section 6: Incompletely-Specified Synchronous Sequential Circuits
Designing IncompletelyDesigning IncompletelySpecified State Machines
Specification: Same as for completelyspecified II. Circuit Modeling: Same as for completel
ECE ECE 3504 Digital Design 1
Section 5g: Timing Considerations
Delays Delays
In logic circuits, all timing In considerations are founded on the notion that certain delays must exist between the occurrences of th certain events.
1 0 1
1 0
Delays Delays i
ECE ECE 3504 Digital Design 1
Section 5f: One-Hot Code State Assignments
One One-Hot Codes
An n-bit code is a one-hot code if An exactly one of the n bits equals one. There are n n-bit one-hot codes. We can make a state assignment that uses only one-hot
The question: On page 518 of the text, how did Figure 8.19 go from table (a) to table (b)? * This is a very good question, and one that finds us trying to understand the difference between design and analysis. Design is a forward process, and one that inv
Quiz 13 ROM Table A designer uses a PROM having 8 addresses and 4 bits per address to implement the excitation and output equations of a sequential circuit. This means that the PROM has 3 input address lines and 4 output data lines. The sequential circuit
Quiz 12 ROM Table
Address Input A3 A2 A1 A0
Input Variable A B C D
Data Output D3 D2 D1 D0
Function W X Y Z
For all functions, A is the most significant input variable, and D is the least significant input variable. Address (Hex) 0 1 2 3 4 5 6 7 8 9 A B C