Digital Design Lab
CSCE2114
Lab#1
Note: Lab problems for today are at the bottom of this document.
Introduction
In this lab you will be working with digital integrated circuit (IC) chips using trainer
Digital Design (CSCE 2114) Lab 8
In this lab you are to write VHDL code to implement a rising edge triggered T flip-flop that has
an asynchronous active low reset input.
The signal names are to be:
Cl
Digital Design (CSCE 2114) Lab 6
Objective:
1. Learn how to write VHDL code to implement some simple combinational circuits.
2. Learn how to simulate your design before implementing it on the FPGA to
Digital Design (CSCE 2114) Lab 5
Objectives:
Learn how to use the Mega Function Wizard to design a complex circuit, like an
adder/sub.
Learn how to simulate your design before implementing it on the
CSCE2114 Digital Logic Lab 4
In this lab, We want write a VHDL code to convert BCD numbers to the corresponding 7segment displays and then download it on FPGA.
You will write a VHDL code of a circuit
HomeworkSet#7
CSCE2114DigitalDesign
Spring2016
Due:Friday,April15,2016
50Points
1) (5 points) Given that the CLK and D waveforms shown below are applied to a gated D
latch,showtheresultingQwaveform.Qi
Homework Set #7
CSCE2114 Digital Design
Spring 2016
Due: Friday, April 15, 2016
50 Points
1) (5 points) Given that the CLK and D waveforms shown below are applied to a gated D
latch, show the resultin
Homework Set #3
CSCE2114 Digital Design
Spring 2016
Due: Wednesday February 24, 2016 (at the start of class)
35 Points
Show the details of your solutions.
1) (5 points) Draw a transistor level schemat
Homework Set #4
CSCE2114 Digital Design
Spring 2016
Due: Wednesday, March 2, 2016
60 Points
1) (5 points) Use a Karnaugh to minimize the following in SOP form:
F(A, B, C) = m(2,3,4,5,6,7)
2) (5 points
Digital Design
Registers and Counters
Design DFF with Functionality
Example: Design a DFF that operates
according to the following transition table,
in which Q+ refers to the state of Q after
the risi
Digital Design
Combinational Logic Design
Construct 2-Variable Karnaugh
Map from min/MAX terms
2-variable K-map Example: F
B
F
01
10
1. Two Adjacent cells have only 1 bit
different from each other. 2.
Digital Design
Mealy and Moore Machine
Design and Optimization
Mealy State Machines
Mealy machines are state machines whose
outputs depend on present state as well as
inputs.
Mealy Machine
Inputs
Pres
Digital Design
CMOS Logic Design
CMOS
CMOS - Complementary Metal Oxide
Semiconductor.
CMOS logic gates are implemented with
Field Effect Transistor(FET).
FET
G
G
G
G
NFET PFET
G=0 OFF G=1 ON
G=1 OFF G
Digital Design
Digital Hardware
Compatator Design
Question: Design a minimal implementation
of the following 3-bit comparator:
Analysis: F(0) = 1 only if A < B F(1) = 1 only
if A > B
A(2:0)
3-bit
B(2:
Digital Design
Computer Arithmetic
Decimal to Twos Complement
Binary Conversion
Example: Convert 5 to twos complement
binary Analysis and Solution: 1. 5 is positive
2. convert its absolute value to bi
Digital Design
Boolean Algebra
Truth Table
Inputs A B C Output F
Truth table lists all input combinations
with corresponding outputs.
00010010010001101000
101011001111
NOT Gate
FFF
F = A
AF
01
10
A
F
CSCE2114 Digital Design
Homework Set #1
DUE: Monday, Feb. 8th, 2016 (at the start of class)
(30 points total)
Show your work. You may use the following table for your conversions as needed, but
show d
Homework Set #2
CSCE2114 Digital Design
Spring 2016
Due: Wednesday, Feb. 17, 2016
50 Points
1) (10 points) Given: F(A,B,C) = (A + B + C) (A + B + C) (A + B + C) (A + B + C)
Show the truth table for F
Homework Set #5
CSCE2114 Digital Design
Spring 2016
Due: Friday, April 1, 2016
45 Points
For the following problems you need to show details of conversions and calculations.
1) (10 points) Convert the
Digital Design
Memory Elements
Latch and Flip-Flop
Latch: level-sensitive
Active high SR latch
Active low SR latch
Active high clocked SR latch
Clocked D latch
Flip-Flop: edge-sensitive
Edge triggered