ECE341 Homework No. 6 Solution
Problem No. 1
(a) There are two data dependencies in the given instruction sequence:
The Subtract instruction depends on the Add instruction for register R3s value
The Subtract instruction depends on the Or instruction for r
ECE341 Homework No. 4 Solution
Problem No. 1
(a) A = 1010, B = 0011
(b)
Problem No. 2
(a) For processor P1: All instructions are fetched from memory
Number of instructions (N) = (700 200) + (200 * 5) = 1500
Cycles per instruction (CPI) = 80
Clock Rate (R)
ECE341 Homework No. 7 Solution
Problem No. 1
Percentage of branch instructions in the program = 20%
Percentage of branch instructions that are taken = 70%
For processor R1:
Since the branch predictor always predicts a not-taken branch, it will incur a pen
ECE341 Homework No. 4
Due date: 05/3/2012
Problem No. 1 (10 points)
(a) Using manual methods, perform the operation A/B (A divided by B) on the 4-bit unsigned
numbers A = 1010 and B = 0011.
(b) Show how the division operation in part (a) would be performe
ECE341 Homework No. 5 Solution
Problem No. 1
Using the same field locations for all instructions enables the processor to read the source registers of an
instruction, while it is still decoding the instruction OP code. Performing the instruction decode an
ECE 341
Lecture # 18
Instructor: Zeshan Chishti
[email protected]
June 5, 2012
Portland State University
Announcements
Final exam is on Thursday, June 14 from 10:15 AM to 12:05 PM
Open book, open notes
Similar format and rules as the midterm
60-70% cove
ECE 341
Lecture # 17
Instructor: Zeshan Chishti
[email protected]
May 31, 2012
Portland State University
Lecture Topics
The Memory System
Cache Memories
Mapping Functions
Examples
Replacement Algorithms
Performance Considerations
Hit Ratios and Mi
ECE 341
Lecture # 15
Instructor: Zeshan Chishti
[email protected]
May 24, 2012
Portland State University
Lecture Topics
Pipelining
CISC Processors
The Memory System
Basic Concepts
Semiconductor RAM Memories
Organization of Memory Devices
Static RA
ECE 341
Lecture # 16
Instructor: Zeshan Chishti
[email protected]
May 29, 2012
Portland State University
Lecture Topics
The Memory System
Read-only Memories (ROM)
Types of ROMs
Memory Hierarchy
Cache Memories
Locality of Reference
Cache Hits
Cache M
ECE341 Homework No. 8 Solution
Problem No. 1
Block size = 128 bytes = 27 bytes = 27 words (since 1 word = 1 byte)
Therefore, Number of bits in the Word field = 7
Cache size = 256K-byte = 218 bytes
Number of cache blocks = Cache size / Block size = 218/27
ECE341 Homework No. 2 Solution
Problem No. 1
The modified shift register is as follows:
Problem No. 2
(a)
1, 2, 3, 4
1. 2. 3
2. 3. 4
2. 3
We choose x1, x2 and x3 as selector inputs.
The resulting 8-input multiplexer circuit is as follows:
(b) We choose x2
Practice Problems for Week-5 (Lectures 9 and 10)
NOTE: There is no homework due in Week 6 due to the midterm exam. The problems in this document
are related to the material that was covered in class during lectures 9 and 10. These problems are provided
to
ECE 341 Midterm Exam Solution
Problem No. 1
(a) False, (b) True, (c) False, (d) False, (e) True, (f) False
Problem No. 2
(a) The state machine for the given counter is as follows:
OR
(b) The state-assigned state table is as follows:
Next State
Present Sta
ECE 341 Midterm Exam
Name: _
Time allowed: 90 minutes
Total Points: 70
Problem No. 1 (9 points)
For each of the following statements, indicate whether the statement is TRUE or FALSE:
(a)
(b)
(c)
(d)
Associative rule applies to both the AND and NAND operat
ECE 341 Final Exam
Name: _
Time allowed: 2 hours
Total Points: 100
Points Scored: _
Problem No. 1 (10 points)
For each of the following statements, indicate whether the statement is TRUE or FALSE. Each correct
answer carries 2 points. The answer for the l
ECE 341 Final Exam Solution
Name: _
Time allowed: 2 hours
Total Points: 100
Points Scored: _
Problem No. 1 (10 points)
For each of the following statements, indicate whether the statement is TRUE or FALSE. Each correct
answer carries 2 points. The answer
ECE 341
Lecture # 14
Instructor: Zeshan Chishti
[email protected]
May 22, 2012
Portland State University
Lecture Topics
Pipelining
Structural Hazards
Pipeline Performance
Effects of Stalls and Penalties
Number of Pipeline Stages
Superscalar Operati
ECE 341
Introduction to Computer
Hardware
Instructor: Zeshan Chishti
[email protected]
Spring 2012
Portland State University
When and Where?
When: Tuesdays and Thursdays 12:00 - 1:50 PM
Where: EB 102
Office hours: Tuesdays and Thursdays after class, or b
ECE341 Homework No. 7
Due date: 05/31/2012
Problem No. 1 (15 points)
Two 5-stage pipelined RISC processors R1 and R2 are used to execute a program P1. 20% of the dynamic
instructions in program P1 are branch instructions and 70% of all the branches are ta
ECE341 Homework No. 8
Due date: 6/7/2012
Problem No. 1 (4 points)
A computer system uses 40-bit memory addresses. It has a 256K-byte cache organized in a direct-mapped
manner, with 128 bytes per cache block. Assume that the size of each memory word is 1 b
ECE341 Homework No. 1
Due date: 04/12/2012
Problem No. 1 (10 points)
Prove the following two distributive rules by using truth tables:
(a) w(y + z) = wy + wz
(b) w + yz = (w + y)(w + z)
Problem No. 2 (10 points)
Prove the following identities by using alg
ECE341 Homework No. 6
Due date: 05/24/2012
Problem No. 1 (20 points)
Consider the following sequence of instructions being processed on the pipelined 5-stage RISC processor
discussed in class:
Add R3, R1, R2
Or R6, R4, R5
Subtract R7, R3, R6
Initially, re
ECE341 Homework No. 5
Due date: 05/17/2012
Problem No. 1 (5 points)
(Problem 5.3 from textbook): Figure 5.12 (also shown on slide 16 of Lecture 9) shows the bit fields
assigned to register addresses for different groups of instructions. Why is it importan
ECE341 Homework No. 2
Due date: 04/19/2012
Problem No. 1 (10 points)
(Problem A.22) Figure A.32 shows a shift register network that shifts the data to the right one place at a
time under the control of a clock signal. Modify this shift register to make it
Problem # 1
A computer system uses 16-bit memory addresses. It has a 2K-byte cache organized in a direct-mapped
manner with 64 bytes per cache block. Assume that the size of each memory word is 1 byte.
(a) Calculate the number of bits in each of the Tag,