Name _
ECE-200 Intelligent Systems
July 25, 2007
Midterm Exam
Closed Book
Instructions: Show your work to receive full credit.
This exam is closed book and notes. You may use a one-page formula sheet.
Problem 1. (15 points)
a) Convert 65 (base 10) to base
ECE 200 Digital Logic Design
Drexel University
Spring 2013-2014
Homework #6 Solutions
6-1 (only b, c, d)
b.
x
1 1 0 1 0 1 0 1 0 0 1 0 1 1
q
A B B C D C D C D C A B C D B
z
0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 0
After the last input, state B goes to either C or B
ECE 200 Digital Logic Design
Drexel University
Spring 2012-2013
Homework #4
Due: Wednesday May 22, 2013, IN CLASS
Textbook Problems:
1) 5.10.2
2) 5.10.3
3) 5.10.4
4) 5.10.5
5) 5.10.14
6) 5.10.17 (b and c)
7) 5.10.19
8) Repeat 5.10.17(c) using a 4x1 MUX an
ECE-200 Week #5
http:/learn.dcollege.net
Dr. Naga Kandasamy
603 Bossone
215-895-1996
[email protected]
Office Hours: Monday 4:00-5:00 pm, or by
appointment
Slides courtesy of Prof. Kurzweg, ECE
Announcements
Midterm is on Wednesday, May 8, IN CLASS
P
ECE 200 Digital Logic Design
Drexel University
Spring 2012 - 2013
Homework #2
Due: Wednesday April 17, 2013 IN CLASS
Show all your work. Points will be removed for answers without work.
Please staple and write your section number on your homework.
1) Prov
ECE 200 Digital Logic Design
Drexel University
Spring 2012 - 2013
Solutions to homework set #2
1) Prove the following simplification theorems using Boolean algebra. State what
theorems that you use.
a) ( X + Y )( X + Y )= X
b) X ( X + Y )= X
c) ( X + Y )
ECE 200-Digital Logic
Drexel University
Winter 2012-2013
Solution Set for Homework #3
Problem 3.8.2
c)
h = a' b' + b c' + a c, or h = a' c' + a b + b' c
g)
f = abd + acd + bd + bc
or f = bcd + acd + bd + ab
h)
g = w' y + y z + w x y' + w x' z'
or g = w' y
EC262 Digital Systems Fall 2011 Chapter 2 Solutions
Textbook: Marcovitz, Introduction to Logic Design, 3rd ed.
Exercise 2 (e and f), Exercise 3(b), Exercise 5 ( a and c), Exercise 8 ( b, e and h), Exercise 9 ( a and b), Exercise 10 (a and b), Exercise 11
Exercises
1. Draw a finite state machine for each of the following cases:
i) A machine with a single binary input that generates an output when the sum of the bits
received so far mod 3 is 0.
0
t h r e e 1 's
0
1
one 1
1
1
t w o 1 's
0
ii) A machine to re
ECE-200 Spring 2012 - 2013
Digital Logic Design
Week 1: Lectures 1 & 2
Introduction, number systems, and arithmetic operations
Prof. Naga Kandasamy
ECE Department
Drexel University
Slides courtesy of Prof. Timothy Kurzweg, Electrical and
About the Course
ECE-200 Weeks #9 and #10
Chapter 7
http:/learn.dcollege.net
Dr. Naga Kandasamy
603 Bossone
215-895-1996
[email protected]
Office Hours: Monday 4:00-5:00 pm or by appointment
Slides courtesy of Prof. Kurzweg, ECE
Example 2: A Sequence Detector
Design a
Drexel University
Spring 2014-2015
ECE 200 Digital Logic Design
Homework #1
Due: Wednesday April 8 IN CLASS
Show all work. Points will be removed for answers without work. Staple
and put your section number on your homework.
1) Describe the behavior of th
Midterm
ECE 200
1 hour
NAME _
1
4
2
5
3
6
sum1
sum2
total
Midterm solution
ECE 200
1.
a) 5 points
Convert 21023 to base 9 without going through base 10. Show your method.
32 = 9, thus can group by 2s:
21 = 2*3 + 1*1 = 7
02 = 0*3 + 2*1 = 2
Thus 21023 =729.
ECE 200 Digital Logic Design
Drexel University
Spring 2012- 2013
Homework #6
1. Draw a state diagram for an FSM that has an input X and an output Y. Whenever
X changes from 0 to 1, Y should become 1 for two clock cycles and then return to
0, even if X is
ECE 200 Digital Logic Design
Drexel University
Spring 2012- 2013
Homework #6
1. Draw a state diagram for an FSM that has an input X and an output Y. Whenever
X changes from 0 to 1, Y should become 1 for two clock cycles and then return to
0, even if X is
ECE 200 Digital Logic Design
Drexel University
Spring 2012 - 2013
Homework #5
Due: Wednesday, June 5, IN CLASS
Show all work. Points will be removed for answers without work.
For the following problems, assume that an implicit rising clock is ANDed with e
ECE 200 Digital Logic Design
Drexel University
Spring 2014-2015
Instructor:
Dr. Baris Taskin
413F Bossone Building
215-895-5972
[email protected]
Office Hours: By appointment only
Recitation Instructors:
Dr. Mark Hempstead
413B Bossone Building
mhemps
ECE 171: Introduction to Digital Circuits
Fall 1999
Lecture Notes 10
Last Time
Project1Assigned
4MoreBARules
TT
POS
Simplifyw/BA
KarnaughMaps
Introduction
2,3,&4Variables
ReviewofExam1
NORLD
This Time
BooleanAlgebra-4MoreRules
Factoring
KarnaughMaps
ECE 200: Digital Logic Design
Introduction Lab: AND Gate
Lab Instructor: Prof. Baris Taskin, ECE Department, Drexel University
1. Objective: Simulation AND gate in ModelSim using VHDL. Setup and simulate 2-input
AND using ModelSim. Follow the ModelSim tut
ECE 200: Digital Logic Design
Lab Assignment # 5: Sequential Logic Design
Name:
1
Date:
Time:
Simulations to verify a D-Latch
Simulate a D-Latch using behavioral VHDL code in ModelSim and verify the truth table.
Sequential circuit, is a type of circuit th
ECE-200 Week #3
http:/learning.dcollege.net
Dr. Timothy P. Kurzweg
313 Bossone Building
215-895-0549
[email protected]
Office Hours: Tuesdays 3:00-5:00 or
by appointment
Kurzweg, Digital Logic Design 2009, Drexel University
Announcements
HW #2 Due W
ECE 200: Digital Logic Design
Lab Assignment # 1: Basic Gates
Name: Date: Time:
1 Simulating A Basic Logic Gate
Simulate a 2 input AND gate in ModelSim using VHDL.
Hint: The objective of this exercise is to show that you can set up two input waveforms for
ECE 200: Digital Logic Design
Lab Assignment # 3: Adder Design
Name:
1
Date:
Time:
Simulations to verify a Half Adder
Simulate a Half Adder in ModelSim and verify the truth table for the SUM and CARRY.
Hint: The objective of this excercise is to design a
ECE 200: Digital Logic Design
Lab Assignment # 4: Multiplexer Design
Name: Date: Time:
1 Simulations to verify a 4:1 Multiplexer using NAND gates
Simulate a 4 input multiplexer using the structural VHDL code in ModelSim and verify the
truth table (write t
ECE 200: Digital Logic Design
Lab Assignment # 4: Multiplexer Design
Name:
1
Date:
Time:
Simulations to verify a 4:1 Multiplexer using NAND gates
Simulate a 4 input multiplexer using the structural VHDL code in ModelSim and verify the
truth table (write t
ECE 200 Digital Logic Design
Drexel University
Fall 2016-2017
Instructor:
Dr. Timothy Kurzweg
601 Bossone Building
215-895-0549
[email protected]
Office Hours: Wed 1:00-3:00PM or By Appointment
Lab Instructors:
Dr. Baris Taskin
413F Bossone Building
ECE 200: Digital Logic Design
Lab Assignment # 5: Sequential Logic Design
1
Simulations to verify a D-Latch
VHDL code for a D-Latch.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity D_Latch is
port(D, CLK : in std_logic;
Q : out std_logic);
end D_Latch;
ECE 200: Digital Logic Design
Lab Assignment # 4: Multiplexer Design
1
Simulations to verify a 4:1 Multiplexer using NAND gates
VHDL code for a 4:1 Multiplexer using NAND gates.
library ieee;
use ieee.std_logic_1164.all;
-Create a 2 input NAND gate simila