ECE
South Dakota School of Mines &Technology
CENG 342/342L Digital Systems
Spring 2017
Catalog Data: CENG 342/342L Digital Systems (3-1) 4 credits.
Prerequisites: CENG 244.
Present the basic concepts and mathematical tools that are applicable to the analy
CENG 342 Digital Systems
Instructor: Dr. Yanxiao Zhao
Lecture 13
Regular Sequential Circuit
D FF and register
Sequential Circuit
Combinational circuit: produce an output based on inputs only. No
memory (dependence on past values of their inputs)
Sequent
Getting Started with ISE Design Suite (14.7)
I: Simulation
CENG 342 Digital Systems
The steps to getting started with a new project with ISE Design Suite are as follows:
Step 1: Go to File and Select New Project.
Step 2: After Selecting the New Project se
ECE
South Dakota School of Mines &Technology
CENG 342/342L Digital Systems
Spring 2016
Catalog Data: CENG 342/342L Digital Systems (3-1) 4 credits.
Prerequisites: CENG 244.
Present the basic concepts and mathematical tools that are applicable to the analy
CENG 342 Digital Systems
Instructor: Dr. Yanxiao Zhao
Lecture 1 Review
Notice: Most notes, figures, and source codes are from textbook
Xilinx ISE Design Installation
Start early, it may take hours
Download:
Search for Xilinx ISE Design suite
http:/www.x
CENG 342 Digital Systems
Instructor: Dr. Yanxiao Zhao
Lecture 7 Routing with a process
Process
Process: statements inside a process are executed
sequentially.
For synthesis, two main purposes:
Describe routing structures with if and case statements
Co
CENG 342 Digital System/Lab
Lab Assignment 3
(Assign: Mar 2, 2016, Due: Mar 14 , 2016)
4-bit mod-13 Counter
A 4-bit mod-13 counter will count from 0 to 12, ignore 13 to 15, and start over again. A reset
signal, a pause signal are included as well. The res
CENG 342 Digital Systems
Instructor: Dr. Yanxiao Zhao
Lecture 24 Debouncing Circuit
Debouncing Circuit
When pressing the switches on S3 board, those switches may
bounce back and forth several times before becoming stable.
Debouncing circuit: to filter o
CENG 342 Digital Systems
Instructor: Dr. Yanxiao Zhao
Lecture 18
LED time-multiplexing circuit
LED time-multiplexing circuit
S3 board has four 7-segment LEDs. They share 8 common signals
to light the segments.
The time-multiplexing schedule enables 1 LE
CENG 342 Digital System Quiz 1
Student ID #1 Major:
1. Complete the truth tables for 2-to-4 binary decoder and 3-to-8 binary decoder as below:
2-to-4 binary decoder with enable signal 3-to-8 binary decoder _V dlsalalll /\ 901552; WW
2. Assume the enti
CENG 342 Digital Systems
Instructor: Dr. Yanxiao Zhao
Lecture 29 Multiplication Circuit
Multiplication Circuit
Some arithmetic operations like division, multiplication, mod, cannot
be synthesized automatically by some software.
Different binary multipli
CENG 342 Digital Systems
Instructor: Dr. Yanxiao Zhao
Lecture 3 Gate-level Combinational Circuit
Demonstrate: 1-bit equality comparator
How to use Xilinx ISE create and simulate VHDL code
TestBench
VHDL code can be simulated in a computer to verify the
CENG 342 Digital Systems
Instructor: Dr. Yanxiao Zhao
Lecture 14
Register
Review: Representing Clock Edges in VHDL
A clock change is represented using:
CLK' event
Which returns 'true after the change to the clock.
For a positive edge:
CLK' event and CLK
CENG 342 Digital System/Lab
Lab Assignment 6
(Assign: April 20 2016, Due: May 1 2016)
The objective of this lab is to design a simple version of the MIPS processor core that can
implement a small subset of its instruction set. This can be designed as a FS
CENG 342 Digital Systems
Instructor: Dr. Yanxiao Zhao
Lecture 27 Debouncing Circuit using FSMD
FSMD Code (Improved debouncing circuit)
The previous design of debouncing circuit uses an FSM and a timer. They are
running independently.
Improved debouncing c
CENG 342 Digital Systems
Instructor: Dr. Yanxiao Zhao
Lecture 3 Gate-level Combinational Circuit
TestBench
VHDL code can be simulated in a computer to verify the
correctness and synthesized to a physical device.
A special program is created to mimic a p
CENG 342 Digital Systems
Instructor: Dr. Yanxiao Zhao
Lecture 4 PLD and Xilinx ISE Overview
Programmable Logic Devices (PLD)
A programmable logic device (PLD) is a component to
build reconfigurable digital circuits. It is different with
logic gates, whic
CENG 342 Digital Systems
Instructor: Dr. Yanxiao Zhao
Lecture 9 Hexadecimal digit to seven-segment LED decoder
7-segment LED display
7-segment LED is configured active low (segment is lit
when the control signal is 0)
Hexadecimal digit to 7-segment LED de
CENG 342 Digital Systems
Instructor: Dr. Yanxiao Zhao
Lecture 5 RT-Level Combinational Circuit
TA information
Name: Jacob Chamber
E-mail: [email protected]
RT-Level Description
Gate-level Design
RT-level Design (module-level)
Adders
Comparat
CENG 342 Digital Systems
Instructor: Dr. Yanxiao Zhao
Lecture 19 Stopwatch
Stopwatch
The watch displays the time in three decimal digits counting from
00.0 to 99.9 and wraps around.
A synchronous clear signal denoted by clr, which reset to 00.0
An enab
CENG 342 Digital Systems
Instructor: Dr. Yanxiao Zhao
Lecture 24 Debouncing Circuit
Debouncing Circuit
When pressing the switches on S3 board, those switches may
bounce back and forth several times before becoming stable.
Debouncing circuit: to filter o
CENG 342 Digital System
Homework Assignment 3
(Assign: Feb 10, 2016, Due: Feb 17, 2016)
1. Page 69
3.9.1 1) 2)
2.
Signed integer to floating-point conversion
A number may need to be converted to different formats in a large system. Assume that
we use the
CENG 342 Digital Systems
Instructor: Dr. Yanxiao Zhao
Lecture 17 Examples
Mod-m and Gray Code Counters
Mod-m Counter
A mod-m counter counts from 0 to m-1 and wraps around.
Example: mod-6 counter
0
5
State diagram
The same direction to each path
4
Only h
CENG 342 Digital Systems
Instructor: Dr. Yanxiao Zhao
Lecture 16 Examples
Counter
Counter
A counter is a sequential circuit whose output
progresses in a predictable repeating pattern, advancing
by one state for each clock pulse.
Binary counter: it has a
CENG 342 Digital Systems
Instructor: Dr. Yanxiao Zhao
Lecture 33 Hierarchical Design
Hierarchical Design
Hierarchical structure: the system is gradually divided into smaller
parts. With a hierarchy, we only need to focus on a small,
manageable part at a
CENG 342 Digital Systems
Instructor: Dr. Yanxiao Zhao
Lecture 3 Gate-level Combinational Circuit
TestBench
VHDL code can be simulated in a computer to verify the
correctness and synthesized to a physical device.
A special program is created to mimic a p
CENG 342 Digital System/Lab
Lab Assignment 2
(Assign: Feb 15, 2017, Due: Feb 22 , 2017)
BCD (binary-coded-decimal) Incrementor
The BCD format uses 4 bits to represent decimal digits. For example, 2010 is represented as
0010 0000 in BCD format. A BCD incre
CENG 342 Digital System
Homework Assignment 4
(Assign: Feb 24, 2016, Due: March 4, 2016)
1. In HW1, we have designed a 4-bit greater than circuit. Treat that circuit as a unit under
test (UUT) and use for loop to design stimulus processes in the testbench
CENG 342 Digital System/Lab
Lab Assignment 1
(Assign: Jan 25, 2016, Due: Feb 1 , 2016)
The purpose of this lab is to familiarize students with the basic procedures of development flow
using VHDL. Your VHDL code designed will be verified through simulation
CENG 342 Digital Systems
Instructor: Dr. Yanxiao Zhao
Lecture 32 Simple MIPS Processor
MIPS Processor
(Microprocessor without Interlocked Pipeline Stages)
15-0
Instruction and Instruction set
Instructions: the language to command a computer architecture.