14:332:331 Homework 1 100 points
Problem 1 20 points
Consider a computer with a processor P1 operating at 2.8 GHz, and executing a
program that has a CPI=1.2, and a length of 3.2x106 instructions. Another computer
has a slower processor P2 operating at 2.
14:332:331ComputerArchitecture
Quiz#3Solutions
Problem 1 (30 points) Consider the singlecycle datapath shown in Figure 1 below. The latencies of the
componentsarespecifiedinthetable1.
TABLE1
Component
Latency(ps)
ALU
100ps
Adder
10ps
ALUControlUnit
20ps
S
Electrical and Computer Engineering
Department
14:332:331
Computer Architecture and Assembly
Language
Fall 2014
Professor Grigore (Greg) Burdea Ph.D.
ECE Department, Rutgers University
Office: Core 721, Office Hours TU, FR 1-2 pm
.
Burdea@jove rutgers.edu
Electrical and Computer Engineering Department
Computer Arithmetic
Introduction
Thus far we have learned about signed and unsigned
integers;
We will now learn about real numbers
Addition and subtraction when the result is larger than
can be accommodated b
14:332:331
The Processor
(datapath and pipelining)
Instruction
Memory
PC
Address
Instruction
Write Data
Read
Register
Data
Reg Addr
File
Reg Addr
Read
Data
Reg Addr
Address
ALU
Data
Memory Read Data
Write Data
Review: Design Principles
Simplicity favors r
Programming Methodology II (14:332:351:01) F13
Quiz 1
9/30/2013
Name:_NetID:_
Multiple Choice Questions [5 points]
1.
What is fundamentally wrong with computing the Fibonacci sequence recursively?
a) it has two base cases
b) each call to the function resu
Programming Methodology II (14:332:351:01) Fall 2013
Quiz 3, 11/13/13
Name:_NetID:_
Multiple Choice Questions [7pts]
1. Which of the following class declarations indicates that Ball is a derived class of Sphere?
Answer: b.
class
class
class
class
Sphere:
Programming Methodology II (14:332:351:01) Fall13
Quiz 2, 10/30/13
Multiple Choice Questions [6 pts]
1.
The _ operation of the ADT stack adds an item to the top of the stack.
createStack
push
pop
getTop
Answer: b.
2.
The _ operation of the ADT stack r
Programming Methodology II (14:332:351:01) Fall13
THE FINAL QUIZ, 12/04/13 [MAX SCORE = 22]
Name:_NetID:_
Multiple Choice Questions [8 pts]
1. Which of the following is NOT a property of a complete binary tree of height h?
all nodes at level h 2 and above
Computer Systems: A Programmers Perspective
Instructors Solution Manual 1
Randal E. Bryant
David R. OHallaron
December 4, 2003
1
Copyright c 2003, R. E. Bryant, D. R. OHallaron. All rights reserved.
2
Chapter 1
Solutions to Homework Problems
The text uses
COMPUTER ARCHITECTURE & ASSEMBLY LANGUAGE
14:332:331
Rutgers University
Fall 2016
Quiz 3 Solution
Question1. Consider the following instruction sequence. We want to run this code on pipelined MIPS.
and R2, R1, R10
lw R1, 2(R2)
add R10, R2, R6
lw R6, 10(R1
COMPUTER ARCHITECTURE & ASSEMBLY LANGUAGE
14:332:331
Rutgers University
Fall 2016
Homework 4 Solution
1. Please determine the control signals for the following instructions in the un-pipelined MIPS.
a) andi $t0, $t1, #12
b) lw $t0,12($t2)
c) sw $t4,12($t7
COMPUTER ARCHITECTURE & ASSEMBLY LANGUAGE
14:332:331
Rutgers University
Fall 2016
Solution of Homework 1
Due: Sep.30, 2016
1.
You are on the design team for a new processor. The clock of the processor runs at 500 MHz. The
following table gives instruction
COMPUTER ARCHITECTURE & ASSEMBLY LANGUAGE
14:332:331
Rutgers University
Spring 2016
Homework 3 (Solution)
1. Suppose A = C4 and B = 4D (both in hexadecimal). Show the step by step result multiplying A and B, using
Booths algorithm. Assume A and B are 8-bi
14:332:331Computer Architecture and Assembly Language
FINAL EXAMINATION SOLUTIONS
PROBLEM 1 (35 points)
Consider the pipeline shown in Figure 1. It executes the sequence of instructions:
<before 1>
40 beq $2, $4, 100
44 lw $3, 100($5)
48 add $6, $3, $2
52
Solutions for DLD PRE_REQUISITE TEST (Course 331Computer Architecture)
Fall 2013
Problem 1 (25 points)
From Figure 1,
Problem 2 (25 points)
From the value function of F, the Truth Table is as follow (Only when W=1 and X=0 and Y=1, the value of F is
1):W
Lecture 3
MIPS organization
o Arithmetic instructions to/from the register file
o Load/store word and byte instructions from/to memory
Logical operations for bitwise manipulations
o A NOT = A NOR 0
Conditional operations
o Signed comparison: slt, slti
o U
14:332:331 Homework 2 Solutions
100 points total
Problem 1 (15 points)
Consider the high-level statement D[4]=B[i+j]. Assume that i is in $t1, j in $s3, the
base address of array B is in $t3, and that of array D is in $s0.
(1) Write the corresponding MIPS
14:332:331 Homework 3
100 points total
Problem 1 (30 points)
A is 22 (base 10) and B is 7 (base 10).
(1) Represent A and B as 6-bit unsigned integers (in binary). (8 points)
2210 = 010110 (in binary) = 2^1+2^2+2^4=2+4+16=22
710 = 000111 (in binary) = 2^0+
COMPUTER ARCHITECTURE & ASSEMBLY LANGUAGE
14:332:331
Rutgers University
Fall 2016
Quiz 2
1. Please compile the MIPS assembly code for the following C code? Assume that m and k are passed in
$a0 and $a1 respectively. Assume that result returned in $v0.
int
COMPUTER ARCHITECTURE & ASSEMBLY LANGUAGE
14:332:331
Rutgers University
Fall 2016
Quiz 1 Solution
1. Assuming A and are two integer arrays. The base address of A and B are in register $s0 and $s1,
respectively. Assume that variables i and j are in $s2, an
ENEE 322
Solution
Homework 08
1. (OW 4.21) Compute the Fourier transform of the following signals. Use Matlab to plot x(t)
as well as the magnitude and phase of X(j).
(a) xa (t) = e3|t|
Xa (j) =
0
=
e3|t| ejt dt
e3t ejt dt +
0
e3t ejt dt
0
1
1
=
e(3j)t
+
Department of Electrical and Computer Engineering
Rutgers, The State University of New Jersey
Computer Architecture and Assembly Language Lab
Fall 2015
Lab 1
Machine Language Instructions, warming up with SPIM simulator,
high-to-low level language convers
14:332:331ComputerArchitectureQuiz#4
Solutions
Problem 1 (35 points) Consider the singlecycle datapath shown in Figure 1 below. The latencies of the
componentsarespecifiedintheTable1.
TABLE1
Component
Latency(ps)
ALU
80ps
Adder
8ps
ALUControlUnit
16ps
Shi
14:332:331
The Processor
(datapath and pipelining)
Instruction
Memory
PC
Address
Instruction
Write Data
Read
Register
Data
Reg Addr
File
Reg Addr
Read
Data
Reg Addr
Address
ALU
Data
Memory Read Data
Write Data
Review: Design Principles
Simplicity favors r