HOMEWORK03 GRADING POLICY
Q1:
a.10pts
b.10pts
A hazard-free manner logic diagram(circuit schematic) or logic expression will all be considered correct.
Q2:
a.10pts
b.10pts
c.10pts
d.10pts
For each question, correct K-map is worth 2pts, Prime Implicants 2p
HOMEWORK04 GRADING POLICY
4.25:20pts:
1.reasonable deduction shows that an n-input OR gate can be replaced by (n-1)2-input OR gates. 10pts
2.the same statement can not be made for NOR gates. 5pts Justify the statement. 5pts
4.30:10pts
The possible fewest
HOMEWORK02 GRADING POLICY
Q2.6(10 points): each conversion is worth 1 point.
Q2.7(8 points): each addition is worth 2 points. The carry out of 1 from the MSB cannot be discarded.
Q2.8(4 points): Because b and d cannot be completed as stated in the book, o
HOMEWORK01 GRADING POLICY
Q1(4.1) 8pts
Answers like "FAILURE'*DESIGNER*STUDIED'+NERD*STUDIED"
and "FAILURE'*DESIGNER*STUDIED' or NERD*STUDIED" are all considered correct.
The correct answer should only have one boolean expression or no points will be g
HOMEWORK06 GRADING POLICY
4.34: 10pts
a.5pts The proving process is worth 2pts.
b.5pts The proving process is worth 2pts.
4.35: 30pts
truth table: 10pts
sum-of-products expression: 10pts
AND-OR circuit: 10pts
4.36: 30pts
truth table: 10pts
sum-of-products
4.1
Z = (DESIGNER STUDIED FAILURE) + (NERD STUDIED FAILURE)
4.4
Theorem 6 (Commutativity):
X Y Y+X
=
X+Y
1
0
1
1
0
1
1
1
0
0
0
0
1
1
1
1
4.5
W and X, as well as,Y and Z, must be grouped together in the compliment and they are in the
original function. The
7.12
Excitation Equations
D1 = Q2+Q1
D2= XQ2
X (Output) = Q1+Q2
State (Q1Q2)
A=00
B=01
C=01
D=11
State
X=0
X=1
Output
A
C
D
1
B
C
C
0
C
A
B
1
D
C
C
1
7.18
Excitation Equations
D2=(Q1+D1) (Q1 Q0)=(Q1+Q2) (Q1 Q0)
D1=Q2
D0=Q1
State (Q2Q1Q0)
A=000
B=001
C=010
1. Problem 6.23, p. 510, Wakerly.
The same circuit can be achieved using 2 2-input NAND gates as well as a 2 input OR gates.
Timing delay (worst case) through a 00 and an 32 = 9ns + 8.5ns = 17.5ns
Timing delay (worst case) through a 138, 151, 00, and an 3
332:231 - Digital Logic Design
Homework 1 - due September 14, 2007
Assignment to be submitted at the start of class.
Q1-Q6. Complete Drill Problems 4.1 through 4.6 in the text.
Q7-Q10. Complete Drill Problems 2.1, 2.2, 2.3, and 2.5.
Q11. What is the value
ECE 231 Digital Logic Design
Homework 6
Due before the beginning of class (12:00 NOON, Tue 10/28/2014)
1. Complete the following problems from Chapter 4 in the text:
4.34, 35, 36, 55.
2. Design circuits for the following function:
1). Binary to Gray Conve
Week 1 In-Class Activities (25 points)
- Only THREE problems are now due:
o Problem 1.1 & 1.5 page 21
o Problem 1.9 page 22
Week 2 In-Class Activities (25 points)
o Problems 4.1, 4.2, & 4.3, page 140
None obvious
7,7.67,9,10,11,11,11.33,11,9
6.4,7.8,11,9
ISyE 3104: Introduction to Supply Chain Modeling:
Manufacturing and Warehousing
Instructor : Spyros Reveliotis
Summer 2006
Solutions for Homework #1
ISYE 3104 Summer 2006
Homework 1 Solution
Problem set:
A.
Answer the following questions:
1.
Consider the
Fujiyama Electronics Case Study - Due Week 7
Objective | Project Deliverables | Grading Rubrics | Best Practices
Objective
This case study looks at the behavior of a circuit board process though the use of
Control Charts. At least two Control Charts will
Objective
This case study looks at the behavior of a circuit board process through the use of control charts. At least
two control charts will need to be constructed, and from them you will be asked to provide an assessment
of what you see. A template to
MATH 152 FINAL EXAM December 15, 2014 VERSION D
NAME: : _RUID:
(please print)
SECTION NUMBER: _ LECTURER:
INSTRUCTIONS:
Be sure to show all work, using Calculus techniques from this course. Unsupported
answers will receive no credit!
Notes, books, formula
Digital Logic Design Exam 2 Fall 2014 No Notes! No Calculators
1) LED, PMOS circuit. VF(LED) = 2.0V 10 pts
a.
b.
c.
What position should the switch be in to light the LED. 2 pts.
Determine IR and IDS if S = 1. 4 pts.
Determine IR and IDS if S = 2. 4 pts.
ECE 231 Digital Logic Design
Homework 3
Due before the beginning of class (12:00 NOON)
1. Implement following circuits in a hazard-free manner.
+ AC;
(a) F (A, B, C) = BCP
(b) F (A, B, C, D) = A,B,C,D (0, 4, 5, 6, 7, 9, 11, 13, 14).
2. Draw K-map, show th
ECE 231 Digital Logic Design
Homework 5
Due before the beginning of class (12:00 NOON, Tue 10/21/2014)
Complete the following problems from Chapter 3 in the text:
3.11, 12, 13, 14, 15, 21, 40, 41, 59, 60, 61, 62, 78.
For # 40, set
For # 41, set
= 0.4 ,
=
ECE 231 Digital Logic Design
Prof. K. Dana
Homework 2: Numerical Methods in Computer Vision
The due date for this assignment is Friday Sept 19th, 12:00 in the afternoon,
before class
Submit as a single pdf file to Sakai. Late assignments are not accepted.
6.2
F = S+T+U+V+W+X+Y+Z
6.3
F = (ABC)
6.9
tpLH = 15ns
tpHL= 15ns
6*15ns = 90ns
6.20
6.21
Both inputs are enabled at the same time, which can cause problems with 74*139. This can be
solved by removing one of the inverters connected to 1G or 2G, ensuring th