CS/EE/CoE 260 - Homework 12
Due 12/9/2002
1. Suppose we want to implement the following logic equations. X = AB' + C(B+D) Y = (A' + B)(AC + C'D) Z = A B + CD'
(a) If these equations are implemented with a PROM, how many words must the PROM have and how ma

CSE 260 Digital Computers: Organization and Logical Design
Homework 10
Jon Turner 11/18/2010
1. (20 points) Consider the circuit shown below. Assume that the circuit elements have the following timing characteristics. gate delays can vary from 0.5 ns to 2

CSE 260 Digital Computers: Organization and Logical Design
Homework 9
Jon Turner 11/11/2010
1. (20 points) Consider adding a breakpoint feature to the WashU-2 processor. This involves adding a breakpoint address register (bpAddr) to the console, a mechani

CSE 260 Digital Computers: Organization and Logical Design
Homework 8
Jon Turner 10/28/2010
1. (20 points) The lecture notes describe a program for converting a sequence of decimal digits stored as ASCII characters into an internal value. The program assu

CSE 260 Digital Computers: Organization and Logical Design
Homework 7
Jon Turner 10/21/2010
1. (20 points) In this problem, you are to modify the priority queue module described in the lecture notes. This version will have two logically separate interface

CSE 260 Digital Computers: Organization and Logical Design
Homework 6 Solutions
Jon Turner
1. (20 points) In this problem, you are to design a VHDL module called showHistory which uses the S3 boards LCD display to show the most recent values from a sequen

CSE 260 Digital Computers: Organization and Logical Design
Homework 5
Jon Turner Due 10/7/2010
1. (20 points) In this problem, you are to design a VHDL module called whichWay that implements a state machine that tracks an 8 bit input value, called dIn, an

CSE 260 Digital Computers: Organization and Logical Design
Homework 4
Jon Turner Due 10/23/2010
1. (20 points) The state transition diagram shown below describes a state machine with two inputs, A and B and a single output X. Write a complete VHDL specifi

CSE 260 Digital Computers: Organization and Logical Design
Homework 3
Jon Turner Due 9/16/2010
1. (20 points) Write a complete VHDL specification for a modified version of the calculator module described in the lecture notes. In this version, the clear, l

CSE 260 Digital Computers: Organization and Logical Design
Homework 13 Solutions
Jon Turner April 22, 2008
1. (15 points) The logic diagram below shows an 8 bit ripple-borrow decrement circuit. Draw a logic diagram for an 8 bit borrow-lookahead decrement

CSE 260 Digital Computers: Organization and Logical Design
Homework 13
Jon Turner April 22, 2008
1. (15 points) The logic diagram at left below shows an 8 bit ripple-borrow decrement circuit. Draw a logic diagram for an 8 bit borrow-lookahead decrement ci

CSE 260 Digital Computers: Organization and Logical Design
Homework 12 Solutions
Jon Turner April 17, 2008
1. (4 points) Find complements for the following expressions. (a) (A + B + C D)(B + D ) AB(C+D) + BD (B+D )(A + D)C + BD ) (b) B D + (A D + C)(B + D

CSE 260 Digital Computers: Organization and Logical Design
Homework 12
Jon Turner April 17, 2008
1. (4 points) Find complements for the following expressions. (a) (A + B + C D)(B + D ) (b) B D + (A D + C)(B + D) 2. (4 points) For each expression, list all

CSE 260 Digital Computers: Organization and Logical Design
Homework 11 Solutions
Jon Turner Due 4/15/2008
1. (10 points) Consider the program on page 9-11 and 9-12 of the lecture notes. Suppose the WashU-1 processor is augmented with a direct-mapped instr

CSE 260 Digital Computers: Organization and Logical Design
Homework 11
Jon Turner Due 4/15/2008
1. (10 points) Consider the program on page 9-11 and 9-12 of the lecture notes. Suppose the WashU-1 processor is augmented with a direct-mapped instruction cac

CSE 260 Digital Computers: Organization and Logical Design
Homework 10 Solutions
Jon Turner Due 4/8/2008
1. (10 points) Consider a 32Kx32 SRAM (K means 1024). How many address bits does this memory require? Assuming that the central memory array has the s

CSE 260 Digital Computers: Organization and Logical Design
Homework 10 Solutions
Jon Turner Due 4/8/2008
1. (10 points) Consider a 32Kx32 SRAM (K means 1024). How many address bits does this memory require? Assuming that the central memory array has the s

CSE 260 Digital Computers: Organization and Logical Design
Homework 10
Jon Turner Due 4/8/2008
1. (10 points) Consider a 32Kx32 SRAM (K means 1024). How many address bits does this memory require? Assuming that the central memory array has the same number

CSE 260 Digital Computers: Organization and Logical Design
Homework 9b Solutions
Jon Turner Due 4/1/2008
1. (15 points) In the WashU-1 processor, the memory control signals and the address and data bus signals are defined by synchronous assignments (that

CSE 260 Digital Computers: Organization and Logical Design
Homework 9b
Jon Turner Due 4/1/2008
1. (15 points) In the WashU-1 processor, the memory control signals and the address and data bus signals are defined by synchronous assignments (that is, the as

CSE 260 Digital Computers: Organization and Logical Design
Homework 9a Solutions
Jon Turner Due 3/27/2008
1. (20 points) Create a project for the WashU-1 processor that contains all the components (top, cpu and support). In the sources menu, right-click o

CSE 260 Digital Computers: Organization and Logical Design
Homework 9a
Jon Turner Due 3/27/2008
1. (20 points) Create a project for the WashU-1 processor that contains all the components (top, cpu and support). In the sources menu, right-click on the cpu

CSE 260 Digital Computers: Organization and Logical Design
Homework 8c Solutions
Jon Turner Due 3/25/2008
1. (30 points) Design for a circuit that maintains a set of (key, value) pairs and always makes the (key, value) pair with the median key value avail

CSE 260 Digital Computers: Organization and Logical Design
Homework 8c
Jon Turner Due 3/25/2008
1. (30 points) Design for a circuit that maintains a set of (key, value) pairs and always makes the (key, value) pair with the median key value available as an

CSE 260 Digital Computers: Organization and Logical Design
Homework 8b Solutions
Jon Turner Due 2/18/2008
1. (20 points) Show how you would modify the VHDL for the vgaDisplay module, if you had a larger memory available. Specifically, assume that you can

CSE 260 Digital Computers: Organization and Logical Design
Homework 8b
Jon Turner Due 2/18/2008
1. (20 points) Show how you would modify the VHDL for the vgaDisplay module, if you had a larger memory available. Specifically, assume that you can implement

CSE 260 Digital Computers: Organization and Logical Design
Homework 7 Solutions
Jon Turner
1. (10 points) Determine if the circuit below is subject to internal hold time violations. If so, show how to modify the circuit to eliminate the hold time violatio

CSE 260 Digital Computers: Organization and Logical Design
Homework 7
Jon Turner Due 2/26/2008
1. (10 points) Determine if the circuit below is subject to internal hold time violations. If so, show how to modify the circuit to eliminate the hold time viol

CSE 260 Digital Computers: Organization and Logical Design
Homework 6c Solutions
Jon Turner
1. (15 points) Write a VHDL module that implements a serial in-range circuit. This is a circuit that determines if an input value x is numerically in between two o

CSE 260 Digital Computers: Organization and Logical Design
Homework 6c
Jon Turner Due 2/19/2008
1. (15 points) Write a VHDL module that implements a serial in-range circuit. This is a circuit that determines if an input value x is numerically in between t