W hat do we "really"
want to know?
- Which system
works best in our
- What costs can be
Latency vs. Bandwith
1. V / L gets worse for each
2. Vproc / Lmem gets worse
Data Dependency Graphs and Pipelining
- Multiple jobs
- High throughput
- Is parallelism as high as possible?
- Is timing data dependent?
1-cycle MIPS processor
- Harvard Architecture (two memories)
- clocking PC initiates cycle
- Long Latency
- Low Bandwidth
Multiple levels :
lower miss rate
lower miss rate
lower avg penalty
Expand tag storage:
entry for ev
W e can hide latency if we can
1. Do more work than we do Reads and Writes
2. Re-use things by keeping them handy
- What size is appropriate?
- Is flexibility important?
Can we avoid cold misses?
Any stride in increments of
2^10 X 2^3 Bytes causes
Manufacturing costs drop as expertise grows,
for that process
- better methods
- better equipment
- less waste (time, materials)
Yield = 1 - waste
- #(devices sellable) versus #(devices produced)
- #(devices sellable) versus (cost to produce them)
C and Linking
LC3 C compiler, lcc; hand linking with assembly code; function call interfaces and protocols.
see src/Makefile for instructions:
We also assume gcc is installed.
- cpp/unix.c and string.h
memmove() redefined in unix.c,
LC3 OS basics
LC3 System Start-Up Assumptions
W e will write an OS for the LC3.
What would a real LC3 do at start up?
1. BIOS execution
- PC points to BIOS (Basic IO System).
- POST: Test and initialize hardware.
- BOOT: Read disk block 0 (512B);
Mid-term Exam, 2012 spring, PART II
Two load-store architecture machines, M1 and M2, have the following characteristics:
Loads and Stores
The CPIs are averaged over all inst