Sequential Circuit Timing
t Objectives
This section covers several timing considerations encountered in the design of synchronous sequential circuits. It has the following objectives: s Define the following global timing parameters and show how they can b
ELEC 326: Class project
Kartik Mohanram
1 Introduction
For this project you will design and test a three-digit binary-coded-decimal (BCD) adder capable of adding positive and negative BCD numbers. In the process, you will 1. gain experience with modern CA
COMPUTING SCIENCE
THIRD BASE
Brian Hayes
A reprint from
American Scientist
the magazine of Sigma Xi, the Scientific Research Society
Volume 89, Number 6 NovemberDecember, 2001 pages 490494
This reprint is provided for personal and noncommercial use. For a
Xilinx and Nexys2 Tutorial
Kartik Mohanram Dept. of Electrical and Computer Engineering Rice University, Houston, TX
Verilog synthesis+simulation with Xilinx
Xilinx Project Navigator Icon onyour Desktop
ELEC 326 Digital Logic Design
2
Open a new project c
Implementation of Digital Systems
Robert J. Jump and Kartik Mohanram Dept. of Electrical and Computer Engineering Rice University
Synthesizable Verilog
Last class
Behavioral models for combinational logic
Today
Dont cares and combinational logic synthesis
Elec/Comp 326
Fall 2012
Homework Set 1
1. Because SLC stores one bit in each cell and MLC stores two
bits in each cell:
SLC
ML
C
SLC
MLC
n=8
8
16
n=8
255
65535
n=16
16
32
n=32
32
64
n=16
65535
4294967295
2.
Memory Size (bytes)
1KB
1M
B
1GB
1TB
2^10=1024
2
Elec/Comp 326
Fall 2012
Homework Set 1(c)
7.
A
1
0
0
1
B
0
1
0
1
Y
1
1
1
0
Function: NAND Gate
8.
(i)
Write down a truth table for the gate
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Y
0
1
0
1
0
1
1
1
(ii) (A) Sketch a CMOS transistor circuit f
Homework 2 (Part A)
Due: October 2 2012
1. For the circuit of Figure 1 write down the truth table and a Boolean
equation expressing Y in terms of inputs A, B, C.
AB#
C#
Y#
A#
#
ABC#
B#+#C#
Figure 1: Circuit for Question 1
2 (a) Express the function Y = F(
Homework 2 (Part B)
Due: October 2, 2012
5. Buoyed by his success, Jerry boasts that any Boolean function can be written
in minimal sum-of-products form as the sum of all the prime implicants of the
function. Hah, retorts Tom, still stinging from his earl
Homework 3 (Part A)
Due: Tuesday, November 6th
1. The inverter of Figure 1(a) has the transfer function shown in Figure 1(b).
Determine the equilibrium voltages at the outputs of the two inverters of Figure 1(c). Identify stable and metastable states (if
Homework 4 (Part A)
Due: Tueday, November 27th (5pm DH2022)
1. Design an 8-bit register from positive edge-triggered ip-ops with the following properties:
1. Responds to external signals CLR, SHIFT-RIGHT, and SHIFT-LEFT at
the rising edge of the clock sig
Glitches and Hazards in Digital Circuits
Glitches and Hazards in Digital Circuits
After a moment you change your mind
John Knight
Electronics Department, Carleton University
Printed; March 24, 04
Modified; March 24, 04
1
Glitches and Hazards in Digital C
X(decimal)
Y(decimal)
P (hex)
P(decimal)
Overflow?
Q(hex)
Q(decimal)
Overflow?
(a)
-4806
15070
6D38
2818
NO
B25C
-19876
NO
(b)
32767
-1522
7A0D
31245
NO
85F1
34289
NO
5. Jerry claims one can find the 2s-complement (f2) of a binary
number by subtracting 1
Sequential Circuit Timing
Objectives
This section covers several timing considerations encountered in the design of synchronous sequential circuits. It has the following objectives: Define the following global timing parameters and show how they can be de
Sequential Circuit Design
Objectives
This section deals with the design of sequential circuits including the following: A discussion of the construction of state/output tables or diagrams from a word description or flow chart specification of sequential b
ELEC 326: Digital Logic Design
Kartik Mohanram Dept. of Electrical and Computer Engineering Rice University
Administrivia
Turn in HW 0 Mailing list havoc Downloading notes
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ELEC 326: Digital Logic Desi
ELEC 326
Kartik Mohanram Handed out on Thursday, August 27th , 2009
1 Objectives
The circuits studied in this course are examples of electrical systems. Therefore, these notes will primarily provide an introduction to the general properties and characteri
ELEC 326
Kartik Mohanram Handed out on Thursday, August 27th , 2009
1 Physical properties of gates
Over the next 12 lectures, we will discuss some of the physical characteristics of integrated circuits. It reviews and expands on material covered in Elec 2
Gates Gate: A simple electronic circuit (a system) that realizes a logical operation.
The direction of information flow is from the input terminals to the output terminal. The number of input and output terminals is finite and they carry binary-valued sig
Karnaugh Maps
Objectives
This section presents a technique for simplifying logical expressions. It will: Define Karnaugh and establish the correspondence between Karnaugh maps and truth tables and logical expressions. Show how to use Karnaugh maps to deri
Combinational-Circuit Building Blocks
Objectives
This chapter introduces several logical networks that are useful as building blocks for larger systems. The objectives of this section are to: Discuss naming conventions for digital signals. Define and demo
Flip-Flops
Objectives
This section is the first dealing with sequential circuits. It introduces Flip-Flops, an important building block for most sequential circuits. First it defines the most basic sequential building block, the RS latch, and investigates
Sequential Circuit Analysis
Objectives
This section introduces synchronous sequential circuits with the following goals:
Give a precise definition of synchronous sequential circuits. Introduce several structural and behavioral models for synchronous seque