Jonathan W. Valvano
EE319K Spring 2013 Lab Manual
Page 1
EE319K Laboratory Manual
Univ of Texas at Austin
Bard, Erez, Gerstlauer, Telang, Valvano, Yerraballi
Do not print the entire document; we will be making many changes.
Spring 2013 (4/20/13 version)
T
Chapter 5, Solution 62.
Let v1 = output of the first op amp
v2 = output of the second op amp
The first stage is a summer
v1 =
R2
R2
vi
vo
R1
Rf
(1)
The second stage is a follower. By voltage division
vo = v2 =
R4
v1
R3 + R4
v1 =
R3 + R4
vo
R4
From (1) an
Chapter 5, Solution 60.
The first stage is a summer. Let V1 be the output of the first stage.
10
10
vi vo
v1 = 2v i 2.5v o
5
4
By voltage division,
10
5
v1 =
vo = vo
10 + 2
6
Combining (1) and (2),
5
10
v o = 2v1 2.5v 0
v 0 = 2 v i
6
3
v1 =
vo
= 6 / 10
Chapter 5, Solution 33.
After transforming the current source, the current is as shown below:
1 k
4 k
12 V
+
vi
va
+
2 k
vo
3 k
This is a noninverting amplifier.
3
1
v o = 1 + v i = v i
2
2
Since the current entering the op amp is 0, the source resistor
Chapter 5, Solution 31.
After converting the current source to a voltage source, the circuit is as shown below:
At node 1,
12 v1 v1 v o v1 v o
=
+
3
6
12
At node 2,
v1 v o v o 0
=
= ix
6
6
From (1) and (2),
48
11
v
ix = o =
6k 727.2A
vo =
48 = 7v1 - 3vo
v
Chapter 5, Solution 13.
By voltage division,
90
(1) = 0.9V
va = 100
v
50
vo = o
3
vb = 150
But va = vb
v0
= 0.9
3
vo = 2.7V
vo
v
+ o=
io = i1 + i2 = 10k 150k 0.27mA + 0.018mA = 288 A
Introduction to Embedded Microcomputer Systems
Lecture 1.1
EE319K Introduction to Embedded Systems Course description Introduce embedded microcomputer systems, Flowcharts, Data flow graphs, Call graphs. Useful web sites Valvanos web page http:/users.ece.u
Introduction to Embedded Microcomputer Systems
Lecture 2.1
Recap Embedded system Microcontroller Data Flow graph Overview 9S12 programming TExaS simulator Top down design Introduction to 9S12 programming
Embedded system
Microcontroller Processor Registers
Chapter 5, Solution 74.
Let v1 = output of the first op amp
v2 = input of the second op amp.
The two sub-circuits are inverting amplifiers
100
(0.6) = 6V
10
32
v2 =
(0.4) = 8V
1.6
v v2
6+8
io = 1
=
=
20k
20k
100 A
v1 =
Electron Charge: 1.602E-19 C
Non-Ideal:
Nodal Analysis
P = iv =
VC =
2
=i R
)
Summing
IL =
Conductance: G = = [Siemens]
Resistors in Series and Parallel
Series
Node 1
=0
Node 2
Node 3
Req = R1+ R2+ R3+ R4+ RN
Parallel
=
)
IC =
VL =
VO =
Inductors
)
+
+
=0
Electron Charge:
1.602E-19 C
P = iv = = i2 R
VC =
IC =
VL =
IL =
Conductance: G = =
[Siemens]
The algebraic sum of
currents entering a node
is zero
Nodal Analysis
Resistors in Series and
Parallel
Series
Power to a Capacitor
Req = R1+ R2+
R3+ R4+ RN
VO =
N
Logic Design .Final Exam
.3. -~" r- A- -, h,
Name: QEFVQA- TQMg Kl
1. Time = 180 mins :- -
2. One cribsheet (lettersize). No books, notes, calculators, phones, PDAs, etc. You
should have nothing on the table except for pens / pencils/erasers, the e
Operations with 0 & 1
1. x + 0 = x
1D. x 1 = x
2. x + 1 = 1
2D. x 0 = 0
Three state Buffer
Idempotent laws
3. x + x = x
3D. x x = x
Involution law
4. (x) = x
Laws of complementarity
5. x + x = 1
5D. x x = 0
Tri-state buffer as mux
C
Commutative laws
6.
EE411: Circuit Theory
Second-Order Circuits
Ranjit Gharpurey
Department of Electrical and Computer Engineering
The University of Texas at Austin
Second-Order Circuits
Characterized by second-order dierential equations
d2
d
a 2 y + b y + cy = d
dt
dt
The v
EE411: Circuit Theory
Sinusoids and Phasors
Ranjit Gharpurey
Department of Electrical and Computer Engineering
The University of Texas at Austin
Sinusoids & AC Circuits
AC corresponds to alternating current
Sinusoidal currents are often referred to by alt
EE411: Circuit Theory
Sinusoidal Steady State Analysis
Ranjit Gharpurey
Department of Electrical and Computer Engineering
The University of Texas at Austin
Sinusoids & AC Circuits
Analysis techniques employed for circuits with
DC sources will be utilized
EE411: Circuit Theory
AC Power Analysis
Ranjit Gharpurey
Department of Electrical and Computer Engineering
The University of Texas at Austin
Instantaneous Power
For instantaneous current i (t ) owing into an
element and voltage v (t ) across the element,
EE411: Circuit Theory
Magnetically Coupled Circuits
Ranjit Gharpurey
Department of Electrical and Computer Engineering
The University of Texas at Austin
Self Inductance
Faradays Law: The voltage generated in a coiled
is proportional to the number of turns
Ideal Transformers
An ideal transformer is characterized by
k = 1 or M = L1 L2
L1 , L2 and M
Lossless
A transformer is characterized by
V1 = j L1 I1 + j M I2
(1)
V2 = j M I1 + j L2 I2
(2)
We can write (1) as I1 = (V1 j M I2 ) /j L1
R. Gharpurey
EE411
Row Reduction
Row Echelon Form
Reduced row Echelon
Row Echelon terminology
Let A be a square n n
matrix. Then the following
statements are equivalent.
Aisinvertible.
Aisrowequivalenttothen
bynidentitymatrixIn.
Aiscolumnequivalenttothe
nbynidentitymatrixI
Invertible Matrix
Theorem
Let A be a square n n
matrix. Then the following
statements are equivalent.
That is, for a given A, the
statements are either all true
or all false.
a. A is an invertible matrix.
b. A is row equivalent to
the n n identity matrix
Suppose A is an n x n matrix and b
is a vector in Rn. If the linear
system Ax=b has a unique solution,
then A is invertible. TRUE
-Let A be an n x n matrix. If
rowA=cola, then A is symmetric.
FALSE
-The set S of all vectors v in R4 such
that v(1,2,-1,-1)
Electron Charge:
1.602E-19 C
Nodal Analysis
Power and Energy in an
Inductor
P = iv = = i2 R
VC =
IC =
VL =
IL =
Conductance: G = =
[Siemens]
Resistors in Series and
Parallel
Series
Req = R1+ R2+
R3+ R4+ RN
Parallel
= + + +
=0
Node 1
Node 2
=0
Node 3
)=0
S
Introduction to Embedded Microcomputer Systems
Lecture 3.1
Recap Get the reference materials on 9S12 instructions TExaS simulates hardware and software Overview How numbers are stored on the computer Precision, basis of numbers Unsigned and signed numbers
Introduction to Embedded Microcomputer Systems
Lecture 4.1
Recap Programmer must keep track of format Precision, decimal digits, basis, ASCII Unsigned, signed (2s complement) Big and little endian Overview Architecture, registers Addressing Modes Memory A