Computer Science CSC263H
St. George Campus
February 11, 2016
University of Toronto
Homework Assignment #3
Due: February 25, 2016, by 5:30 pm
You must submit your assignment as a PDF file of a typed (not handwritten)
document through the MarkUs system by

Computer Science CSC263H
St. George Campus
February 25, 2016
University of Toronto
Solutions for Homework Assignment #3
Answer to Question 1. The set S can be implemented as an augmented AVL tree T . Each node u of
T contains the fields:
key: contains th

Barrel Shifter
The Barrel Shifter
The ARM doesnt have actual shift
instructions.
Instead it has a barrel shifter which
provides a mechanism to carry out shifts as
part of other instructions.
So what operations does the barrel shifter
support?
Barrel Sh

ALU is in Datapath
Computer
Processor
Control
Datapath
PC
ALU
R
E
G
I
S
T
E
R
S
Main
Memory
Devices
INPUT
OUTPUT
Datapath performs arithmetic and logical operations on
data (binary #s) via the ALU (Arithmetic Logic Unit)
1
1-bit ALU for AND, OR, ADD
OP CO

ARM Architecture
What are the main features of
ARM architecture?
The Basic ARM Architecture is a 32 Reduced Instruction Set Computer it incorporates
Typical RISC architecture features:
A large uniform register file
A load/store architecture, where data-

Binary integer multiplication
Binary Integer
011
multiplicand (m)
Multiplication
x 0 0 1 multiplier (n)
011
multiply and shift
0 0 0 intermediate
+ 000
products (Pb)
00011
product: (p) m+n bits
For each bit b of nplier, right to left
cfw_
If b=1, Pb = a c

Introduction to Several ARM
processors
(OPTIONAL)
1
ARM7TDMI Processor Core
Current low-end ARM core for applications like
digital mobile phones
TDMI
T: Thumb, 16-bit compressed instruction set
D: on-chip Debug support, enabling the processor to
halt

PIPELINING
Performance Issues
improved by Pipelining
Longest delay determines clock period
Critical path: load instruction
Instruction memory register file ALU data memory register file
Not feasible to vary period for different instructions
Violates desig

How we can avoid the hazard by using a
pipeline interlock?
The pipeline interlock will detect
when data forwarding will not be
able to get the data to the next
instruction in time.
A stall is introduced until the
instruction can get the appropriate
data

The Processor
Structure of von Neumann
machine
Structure of IAS
detail
MQ multiplier quotient register
AC Accumulator
Memory buffer register (MBR)/MDR
stores the data being transferred to and
from the immediate access store
instruction register stores th

How we can avoid the hazard by using a
pipeline interlock?
The pipeline interlock will detect
when data forwarding will not be
able to get the data to the next
instruction in time.
A stall is introduced until the
instruction can get the appropriate
data

Pipeline Hazards
There are situations, called hazards, that prevent the next
instruction in the instruction stream from being executing during its
designated clock cycle. Hazards reduce the performance from the
ideal speedup gained by pipelining.
There ar

COMPUTER ORGANIZATION AND DESIGN
Instruction Level
Parallelism and Dynamic
Execution
Pipeline Basics in Intel 8086
The original 8086 processor has 14 CPU registers which are still in use
today
Each new chip in the 8086 family added new functionality. Mo

PHI 210
Peer evaluation
Name of evaluator:
Author being evaluated:
The goal is to help the author improve their argument by pointing out the strengths and
weaknesses of their paper.
1) Did the author clearly state their thesis? Does the thesis promise a s

Computer Science CSC263H
St. George Campus
January 28, 2016
University of Toronto
Homework Assignment #2
Due: February 11, 2016, by 5:30 pm
You must submit your assignment as a PDF file of a typed (not handwritten)
document through the MarkUs system by l

Computer Science CSC263H
St. George Campus
February 25, 2016
University of Toronto
Homework Assignment #4
Due: March 10, 2016, by 5:30 pm
You must submit your assignment as a PDF file of a typed (not handwritten)
document through the MarkUs system by log

Computer Science CSC263H
St. George Campus
March 10, 2016
University of Toronto
Homework Assignment #5
Due: March 24, 2016, by 5:30 pm
You must submit your assignment as a PDF file of a typed (not handwritten)
document through the MarkUs system by loggin

Computer Science CSC263H
St. George Campus
January 28, 2016
University of Toronto
Solutions for Homework Assignment #1
Answer to Question 1.
a. T (n) is O(n2 ). This is because for every n > 2:
(i) For every input array A of size n, the outer for loop of

Computer Science CSC263H
St. George Campus
March 10, 2016
University of Toronto
Solutions for Homework Assignment #4
Answer to Question 1. First we make some observations common to both sub-questions. The value of
x at the completion of the algorithm is i

Computer Siene 263/B63
Design and Analysis of Data Strutures
University of Toronto
NOTES ON AVL TREES
by Vassos Hadzilaos
Binary searh trees work well in the average ase, but they still have the drawbak of linear worst ase time
omplexity for all three ope

CSC263H
Data Structures and Analysis
University of Toronto
Note on MST
MST Construction Theorem
The following theorem shows how one can extend any spanning forest of a graph G that is
contained in some MST of G, into a larger forest that is also contained

CSC263H
Data Structures and Analysis
University of Toronto
Note on BFS
BFS(s) Computes the Shortest Paths from s Proof Sketch
Recall that during the execution of a BFS started from s (denoted BFS(s), if a node u
discovers a node v, then d[v] is set to d[u

TIME COMPLEXITY OF ALGORITHMS
Vassos Hadzilacos
University of Toronto
1
Measuring time complexity
The worst-case time complexity of an algorithm is expressed as a function
T : N N
where T (n) is the maximum number of steps in any execution of the algorith

CSC263H
Data Structures and Analysis
University of Toronto
Course Information
Instructor: Sam Toueg
Office: Sandford Fleming 2304C
Office Hours: Friday 10 am - 12 noon, or by appointment
Telephone: 416-946-3510
Email: [email protected]
Course web page:
D

Programming
Techniques
R. Morris
Editor
A Sorting
Problem and
Its Complexity
Ira Pohl
University of California*
A technique for proving min-max norms of sorting
a l g o r i t h m s is given. O n e new a l g o r i t h m for finding the
minimum and maximum

Computer Science CSC263H
St. George Campus
January 14, 2016
University of Toronto
Homework Assignment #1
Due: January 28, 2016, by 5:30 pm
You must submit your assignment as a PDF file of a typed (not handwritten)
document through the MarkUs system by lo