University of California, Berkeley College of Engineering
Department of Electrical Engineering and Computer Science Spring 2004 Instructor: Dan Garcia 20040522
CS61C Final
Last Name First Name Student ID Number Login The name of your TA (please circle
CS61C Spring 2013 HW2: restricted grep (rgrep)
TA: Paul Ruan (modified from hw by Eric Liang, and originally by C onor Hughes)
Due Sunday, February 10, 2013 at 11:59:59PM
Goals
The objective of this assignment is to get you familiar and comfortable with s
CS61C Fall 2012 13 Final Review
One, two, three SIMD! Spring 2011 Final (Katz, Patterson)
a) SIMDize the following code by filling in the spaces provided. Assume n is a multiple of 4.
void count( int n, float *c) cfw_
void countfast( int n, float *c) cfw_
CS61C Fall 2012 13 Final Review
One, two, three SIMD! Spring 2011 Final (Katz, Patterson)
a) SIMDize the following code by filling in the spaces provided. Assume n is a multiple of 4.
void count( int n, float *c) cfw_
void countfast( int n, float *c) cfw_
8/24/12
Agenda
Great Ideas in Computer Architecture
Administrivia
PostPC Era: From Phones to Datacenters
CS 61C: Great Ideas in Computer
Architecture (Machine Structures)
Course Introduc?on
Instructors:
Krste Asanovi
CS61C Fall 2012 5 Caches
Caches
Conceptual Questions: Why do we cache? What is the end result of our caching, in terms of capability?
What are temporal and spatial locality? Give high level examples in software of when these occur.
Break up an address:
Ta
CS61C Fall 2012 3 Intro to C: Pointers, Arrays, and Strings
C vs. Java
For many operations, C is similar to Java. However, there are a number of key differences
between the languages:
Java
C
Object oriented
No objects, inheritance, or polymorphism
Methods
CS61C Fall 2012 1 MapReduce and Warehouse Scale Computers
MapReduce
Divide a large data set into many smaller pieces for independent parallel processing. Combine and
process intermediate results to obtain final result. Execution goes as follows:
0)
1)
2)
CS61C Fall 2012 3 The Formation of Integers and MIPS
The Formation of Integers
Idea
Implementation
Pros
Cons
Unsigned
Start 0 as 0000 0000.
Make 1 into 0000 0001.
Count upwards.
Sign is first bit (1 = , 0 = +)
Other bits are like unsigned.
Continuous.
No
CS61C Fall 2012 4 Everything is a Number!
Floating Point Numbers (IEEE Standard 754)
Why? We need to represent real numbers!
Single precision FP (32 bit):
FP value = (1)S x (1 + F) x 2(E bias)
Sign
Exponent (E)
Fraction (F) / Mantissa
0
23
31
For single
CS61C Fall 2012 3 The Formation of Integers and MIPS
The Formation of Integers
Idea
Implementation
Pros
Cons
Unsigned
Start 0 as 0000 0000.
Make 1 into 0000 0001.
Count upwards.
Sign is first bit (1 = , 0 = +)
Other bits are like unsigned.
Continuous.
No
University of California, Berkeley College of Engineering
Department of Electrical Engineering and Computer Sciences
Summer 2015
Instructor: Sagar Karandikar
20150728
J
L
After the exam, indicate on the line above where you fall in the emotion spectrum
/*
* This is so the C preprocessor does not try to include multiple copies
* of the header file if someone uses multiple #include directives.
*/
#ifndef _HASHTABLE_H_
#define _HASHTABLE_H_
/*
* Everyone uses NULL, or 0, as the null pointer,
* but C never
CS61C Fall 2012 12 ECC & Interrupts
Hamming Codes
Recall the basic structure of a Hamming code. Given bits 1.,m, the bit at position 2^n (starting
at n=0, the first bit) is parity for all the bits with a 1 in position n. For example, the first bit is
chos
CS61C Fall 2012 12 ECC & Interrupts
Hamming Codes
Recall the basic structure of a Hamming code. Given bits 1.,m, the bit at position 2^n (starting
at n=0, the first bit) is parity for all the bits with a 1 in position n. For example, the first bit is
chos
CS61C Fall 2012 11 More Caches & C Memory Management
Set Associative Caches
Similar to Direct Mapped, except that multiple blocks can be stored at each Index. Must look at
ALL tags at a given Index to determine if hit or miss. Must invoke the replacement
10/26/12
You are Here!
CS 61C:
Great Ideas in Computer Architecture
Single Cycle MIPS CPUPart II
So4ware Hardware
Parallel Requests
Assigned to computer
e.g., Search Katz
Harness
Parallel Threads
10/26/12
You Are Here!
CS 61C:
Great Ideas in Computer Architecture
Control and Pipelining
So0ware Hardware
Parallel Requests
Assigned to computer
e.g., Search Katz
Harness
Parallel Threads Parallel
CS61C Fall 2012 6 Midterm Review
Ackermann Spring 2012 Midterm (Patterson)
The Ackermann function A is defined as follows:
Fill in the following C function so that it computes A(m, n).
unsigned int A(unsigned int m, unsigned int n) cfw_
if (_) cfw_
_;
el
CS61C Fall 2012 6 Midterm Review
Ackermann Spring 2012 Midterm (Patterson)
The Ackermann function A is defined as follows:
Fill in the following C function so that it computes A(m, n).
unsigned int A(unsigned int m, unsigned int n) cfw_
if ( m = 0 ) cfw_
CS61C Fall 2012 7 Data and Threadlevel Parallelism
Datalevel Parallelism SIMD

Operate on multiple data with a single instruction
In this class and project 3: Intel SSE Intrinsics
Intel SSE Intrinsics

Special 128bit registers (XXM07; 015 if x86 6
CS61C Fall 2012 8 Combinational Logic and FSM
Combinational Logic
OR
AND
NOT
B
A
A
0
0
1
1
B
0
1
0
1
C
0
1
1
1
A
0
0
1
1
B
0
1
0
1
C
0
0
0
1
A
0
1
B
1
0
Using these above gates, create a NOR gate, a NAND gate, an XOR gate, and an XNOR gate.
Simplify the f
CS61C Fall 2012 8 Combinational Logic and FSM
Combinational Logic
OR
AND
NOT
B
A
A
0
0
1
1
B
0
1
0
1
C
0
1
1
1
A
0
0
1
1
B
0
1
0
1
A
0
1
C
0
0
0
1
B
1
0
Using these above gates, create a NOR gate, a NAND gate, an XOR gate, and an XNOR gate.
NOR
NAND
XOR
X
CS61C Fall 2012 9 State Elements and Single Cycle CPU
State Elements
State elements provide a means of storing values and controlling data flow in a circuit. The most
basic state element is a Dtype FlipFlop (figure 1a). D and Q are single bit input and
CS61C Fall 2012 10 Pipelining and Hazards
Pipelining Hazards:
Structural Hazards that occur due to competition for the same resource (register file read vs. write
back, instruction fetch vs. data read). These are solved by caching and clever register timi
CS61C Fall 2012 10 Pipelining and Hazards
Pipelining Hazards:
Structural Hazards that occur due to competition for the same resource (register file read vs. write
back, instruction fetch vs. data read). These are solved by caching and clever register timi
CS61C Fall 2012 9 State Elements and Single Cycle CPU
State Elements
State elements provide a means of storing values and controlling data flow in a circuit. The most
basic state element is a Dtype FlipFlop (figure 1a). D and Q are single bit input and
University of California, Berkeley College of Engineering
Department of Electrical Engineering and Computer Sciences
Fall 2015
Instructors: John Wawrzynek, Vladimir Stojanovic
20151218
L
J
After the exam, indicate on the line above where you fall in the
University of California, Berkeley College of Engineering
Department of Electrical Engineering and Computer Sciences
Fall 2015
Instructors: Vladimir Stojanovic, John Wawrzynek
20151218
L
J
After the exam, indicate on the line above where you fall in the
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