UNIVERSITY OF CALIFORNIA
College of Engineering
Department of Electrical Engineering and Computer Sciences
EE 105
Spring 2013
Prof. Salahuddin
Homework Assignment #1
Due at the beginning of class on Tuesday, 2/06/13
Problem 1 [20 points]: Intrinsic Semico
UNIVERSITY OF CALIFORNIA
College of Engineering
Department of Electrical Engineering and Computer Sciences
EE 105
Fall 2013
Prof. Wu
Homework Assignment #1
Due date: 5:00pm on Friday, 9/13/2013
Problem 1 [20 points]:
a) Say we take a sample of silicon and
UNIVERSITY OF CALIFORNIA, BERKELEY
College of Engineering
Department of Electrical Engineering and Computer Sciences
EE 105: Microelectronic Devices and Circuits
Spring 2008
MIDTERM EXAMINATION #1
Time allotted: 80 minutes
NAME: _SOLUTIONS_
(print)
Last
S
UNIVERSITY OF CALIFORNIA
College of Engineering
Department of Electrical Engineering and Computer Sciences
EE 105
Spring 2013
Prof. Salahuddin
Homework Assignment #1 Solution
Problem 1
a) The first transistors were fabricated using germanium (Ge) as the s
University of California
College of Engineering
Department of Electrical Engineering and Computer Science
EE 105
Spring 2016
Due Friday 4/22 @ 5PM
Homework Assignment #10
9.56
For the differential amplifier shown in Fig. P9.2, let ! and ! have
! / = 4 mA/
7.6 RD = 20 k
k n
= 200 A/V
1
k n (VGS Vt2 )
2
7.25 (a) ID =
2
VGS = 0.7 V
1
5(0.6 0.4)2 = 0.1 mA
2
VDS = VDD ID RD = 1.8 0.1 10 = 0.8 V
Av = 10 V/V
(b) gm = k n VOV = 5 0.2 = 1 mA/V
Av = k n VOV RD
(c) Av = gm RD = 1 10 = 10 V/V
=
VRD = 1.5 V
1
2
k n VO
University of California
College of Engineering
Department of Electrical Engineering and Computer Science
EE 105
Spring 2016
Due Friday 3/18 @ 5PM
Homework Assignment #7
7.77
A CG amplifier using an NMOS transistor for which gm = 2 mA/V has a 5-k
drain re
7.77 Rin =
Gv =
=
1
1
= 0.5 k
=
gm
2 mA/V
7.95
Rin
gm (RD
RL )
Rin + Rsig
VDD
0.5
2(5
5)
0.5 + 0.75
RG1
= 2 V/V
RD
ID
VG 5 V
For Rin = Rsig = 0.75 k
ID
1
= 0.75 gm = 1.33 mA/V
gm
Since gm = 2k n ID , then to change gm by a factor
1.33
= 0.67, ID mus
University of California
College of Engineering
Department of Electrical Engineering and Computer Science
EE 105
Spring 2016
Due Monday 3/14 @ 5PM
Homework Assignment #6
7.6
Various measurements are made on an NMOS amplifier for which the drain
resistor !
7.126
For an overall gain of 40 V/V,
DC design:
40
vo
=
= 104 V/V
v
0.385
VB = 5 V,
VBE = 0.7 V
But
vo
= gm (RC
RL )
v
VE = 4.3 V
For
IE = 2 mA,
RE =
104 = 73.4 (RC
2)
VE
4.3
= 2.15 k
=
IE
2
(RC
2) = 1.416
5
= 25 k
IR2 = 0.2 mA, R2 =
0.2
IE
2
=
0.0
University of California
College of Engineering
Department of Electrical Engineering and Computer Science
EE 105
Spring 2016
Due Friday 4/1 @ 5PM
Homework Assignment #8
7.126
Using the topology of Fig. P7.125, design an amplifier to operate between a 2-k
University of California
College of Engineering
Department of Electrical Engineering and Computer Science
EE 105
Spring 2016
Due Friday 3/4 @ 5PM
Homework Assignment #5
6.3
In a particular technology, a small BJT operating at !" = 30! conducts a
collector
University of California
College of Engineering
Department of Electrical Engineering and Computer Science
EE 105
Spring 2016
Due Friday 4/8 @ 5PM
Homework Assignment #9
8.55
In the common-gate amplifier circuit of Fig. P8.55, ! and ! are matched.
!
!
! !
University of California
College of Engineering
Department of Electrical Engineering and Computer Science
EE 105
Spring 2016
Homework Assignment #11
(These problems are for your own benefit. You do not need to submit this homework.)
10.5
The amplifier in
9.102 The overdrive voltage, |VOV |, at which Q1
and Q2 are operating is found from
9.56 Refer to Fig. P9.2.
ID = 0.25 mA =
0.25 =
1
W
p Cox
2
L
|VOV |2
1
4 |VOV |2
2
|VOV | = 0.353 V
2 0.25
2ID
gm =
=
= 1.416 mA/V
|VOV |
0.353
| Ad | = gm RD = 1.416 4
EE105 Fall 2015
Microelectronic Devices and Circuits
Prof. Ming C. Wu
[email protected]
511 Sutardja Dai Hall (SDH)
8-1
Circuit Symbol for NMOS
4 terminal including
Body
(Arrow pointing to
channel indicating
substrate is p-type)
Modified circuit symbol
EE105 Fall 2015
Microelectronic Devices and Circuits
Prof. Ming C. Wu
[email protected]
511 Sutardja Dai Hall (SDH)
16-1
Basic BJT Gain Cells with Ideal
Current Source Load
16-2
Basic Gain Cells with Ideal Current
Source Load
16-3
Output Resistance of
EE105 Fall 2015
Microelectronic Devices and Circuits
Prof. Ming C. Wu
[email protected]
511 Sutardja Dai Hall (SDH)
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AC Equivalent Circuit for Common
Mode Input
Non-ideal current source
consists of an ideal current
source shunted by a large
resista
EE105 Fall 2015
Microelectronic Devices and Circuits
Prof. Ming C. Wu
[email protected]
511 Sutardja Dai Hall (SDH)
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I-V Characteristics of BJT
The I-V looks similar to MOSFETs I-V, though the physical
equations governing the saturation (triode fo
EE105 Fall 2015
Microelectronic Devices and Circuits
Prof. Ming C. Wu
[email protected]
511 Sutardja Dai Hall (SDH)
20-1
Two-Stage CMOS Op-Amp Circuit
20-2
Two-Stage CMOS Op-Amp Circuit
Current
Mirrors
Common
Source
Amplifier Stage
Differential Pair
wi
EE105 Fall 2015
Microelectronic Devices and Circuits
Prof. Ming C. Wu
[email protected]
511 Sutardja Dai Hall (SDH)
17-1
How To Increase Voltage Gain?
17-2
Common Gate Amplifier is an
Impedance Transformer
17-3
Common Gate Amplifier is an
Impedance Tra
EE105 Fall 2015
Microelectronic Devices and Circuits
Prof. Ming C. Wu
[email protected]
511 Sutardja Dai Hall (SDH)
11-1
Transistor Operating Mode in Amplifiers
Transistors are biased in flat part of the I-V curves
Saturation mode for MOSFET, and act
EE105 Fall 2015
Microelectronic Devices and Circuits
Prof. Ming C. Wu
[email protected]
511 Sutardja Dai Hall (SDH)
12-1
Basic Single-Transistor Amplifier
Configurations
MOSFET
BJT
12-2
Two-Port Model of Amplifiers
12-3
Common-Source (CS) Amplifier
12-
EE105 Fall 2015
Microelectronic Devices and Circuits
Prof. Ming C. Wu
[email protected]
511 Sutardja Dai Hall (SDH)
7-1
MOSFET
MOSFET: metal-oxide-semiconductor field effect transistor
Typically
Channel length: L ~ 10 nm to 0.35 m,
Channel width: W
MUN Awwm "5"- m
: 5i.
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(SD
1]
cfw_a
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C. Wu
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eccs .berke [V.du
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Wm; ta-tath
: w
gngmm; f
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47% t,
M "'zm
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WM?
* Finite open-100p gain (Am < 96 1
* Finite input resistance (Ri < 35
EE105 Fall 2015
Microelectronic Devices and Circuits
Prof. Ming C. Wu
[email protected]
511 Sutardja Dai Hall (SDH)
18-1
Why Differential?
Differential circuits are much less sensitive to
noises and interferences
Differential configuration enables us