EE 2010
Fall 2010
EE 231
Homework 1
1. Problem 1.1. Instead of Base 13, represent the numbers from 8 to 23 in base 14.
16 to 32, octal and hexadecimal:
1610
1710
1810
1910
2010
2110
2210
2310
2410
2510
2610
2710
2810
2910
3010
3110
3210
208
218
228
238
24
EE 231
Fall 2010
EE 231
Homework 12
Due November 22, 2010
1. Consider the circuit below:
y
x
Q1
J1
J
K1
D0
Q
z
K
DQ
Q0
clock
(a) Is this a Mealy machine or a Moore machine? Explain.
This is a Mealy machine output y depends only both the present state and
EE 231
Fall 2010
EE 231
Homework 13
Due December 3, 2010
1. Explain in words and write the HDL statements for the operations specied by the following
register transfer notations;
(a) R1 R1 1, R2 R1
Transfer the contents of R1 minus 1 into R1; at the same
EE231 Solid State Devices
Professor: Vivek Subramanian viveks@eecs.berkeley.edu 571 Cory Hall (510) 643-4535 Alejandro de la Fuente Vornbrock, adelafv@eecs.berkeley.edu
TA:
Web Page: http:/www-inst.eecs.berkeley.edu/~ee231/ http:/organics.eecs.berkeley.ed
Hot Carrier Effects Reading: Chapter 9
EE231 Vivek Subramanian
Slide 4-1
Why do we care about hot electron effects?
Electron-hole pairs are generated due to energetic carriers in drain depletion region Can be injected into oxide, causing damage / traps D
Advanced MOSFET physics Reading: Chapter 5
EE231 Vivek Subramanian
Slide 3-1
Scaling and its impact on the off-state
EE231 Vivek Subramanian
Slide 3-2
MOS Scaling
Over the years, MOS devices have scaled in size 1970's ~ 10um Today: ~0.12um Reasons Speed
Gate Oxides Physics and Technology Reading: Chapter 7
EE231 Vivek Subramanian
Slide 6-1
The ITRS Roadmap A Preview
Note that we are operating at 50% of dielectric breakdown (~10MV/cm), and are working with thicknesses that we definitely expect to allow tu
EE 231
Fall 2010
EE 231
Homework 11
Due November 15, 2010
1. The memory units that follow are specied by the number of words times the number of bits
per word. How many address lines and input-output data lines are needed in each case?
(a) 32 x 8
32 = 25
EE 231
Fall 2010
EE 231
Homework 10
Due November 5, 2010
1. Design a synchronous sequential circuit which generates the following sequence. (The sequence should repeat itself.)
00000001
00000010
00000001
00000100
00000001
00001000
00000001
00010000
000000
EE 2010
Fall 2010
EE 231 Homework 2
Due September 10, 2010
1. Convert the decimal numbers +75 and +32 to 8-bit hexadecimal numbers, unsing the signed
2s complement representation. Then perform the following operations: (a) (+75) + (32),
(b) (75) + (+32),
EE 2010
Fall 2010
EE 231 Homework 3 Solutions
Due September 17, 2010
1. Find the truth table for the following functions:
(a) F = y z + y z + xz
x
0
0
0
0
1
1
1
1
y
0
0
1
1
0
0
1
1
z
0
1
0
1
0
1
0
1
yz
1
0
0
0
1
0
0
0
x
0
0
0
0
1
1
1
1
y
0
0
1
1
0
0
1
1
z
EE 2010
Fall 2010
EE 231 Homework 4
Due September 24, 2010
1. Find all the prime implicants for the following Boolean functions, and determine which are
essential. Then simplify the expressions.
(a) F (w, x, y, z ) = (0, 1, 4, 5, 5, 7, 8, 9, 13, 15)
yz
00
EE 2010
Fall 2010
EE 231 Homework 5
Due October 1, 2010
1. For the circuit shown in Fig. 4.26 (page 155 of the text),
(a) Write the Boolean function for the outputs in terms of the input variables.
Y0 = (A0 S E )|(B0 SE )
Y1 = (A1 S E )|(B1 SE )
Y2 = (A2
EE 2010
Fall 2010
EE 231 Homework 6
Due October 8, 2010
1. Problem 4.16
Dene the carry propagate and carry generate as
Pi = Ai + Bi
Gi = Ai Bi
respectively. Show that the output carry and the output sum of a full adder becomes
Ci+1 = (Ci Gi + P i )
Si = (
EE 2010
Fall 2010
EE 231 Homework 7
Due October 15, 2010
1. Show how to build a J-K ip-op using a T ip-op and some combinational logic.
A J-K ipop is a synchronous sequential circuit with two inputs (J and K) and one state
ip-op (A). We design this from a
EE 231
Fall 2010
EE 231
Homework 8
Due October 20, 2010
1. Consider the circuit below. It has three inputs (x and clock), and one output (z). At reset,
the circuit starts with the outputs of all ip-ops at 0.
x
z
DQ
J
Q
Q
K
Q
clk
(a) Is this a Mealy machin
EE 231
Fall 2010
EE 231
Homework 9
Due October 29, 2010
1. A serial parity-bit generator is a sequential circuit that does the following: it receives an n-bit
message followed by a 0 (so there are n + 1 clock bits to send the message). At the output,
the