Released December 13, 2013
EECS150/Problem Set 10 Solution
1. Fast up counter.
An up counter has next state decoder NS = PS + 1 . Design a 16 bitCarry Look Ahead
incrementer (add 1) using 4 bit blocks, 2 input gates only. Estim
EECS150/Problem Set 6 Solution
1.1. Synchronization pt 1 (10 pts). The AD9980 video decoder on the XUP board sends
luminance information for each pixel Y[7:0], and timing information HSOUT and VSOUT
using a generated data clock
En Clr D
En Clr D
EECS150/Problem Set Solution
Due at 10 am, Thu. Oct. 3 (homework box under stairs)
1. (25 pts) List Processor Timing. The list processor as discussed in lecture is described in
RT Language as:
1. X Memory[NUMA], NUMA NEXT + 1;
EECS150/Problem Set 3 Solution
Due at 10 am, Thu. Sep. 26
Reading Harris and Harris: 3.4, 4.9
1. (20 pts) Datapath and control I. For the datapath below, determine a sequence of operations which will exchange the contents of Ac
EECS150/Problem Set 7 Solution
1. Video Encoder (35 pts)
Consider the video encoder from Checkpoint 1.
a. Describe in words the operation of the CountRegion.v module.
The CountRegion module is a comparator combined with a state
EECS150/Problem Set 8 Solution
Due at 12 pm, Thu. Nov. 7 (homework box under stairs)
(This problem set may be done in a group of maximum 2 students, with 1 unique writeup to be
turned in per group.)
1. (25 pts) CMOS.
EECS 150 Digital Design Lecture 4 Notes
Only Two Types of Circuits Exist
Combinational Logic Blocks (CL) <= out=f(inputs)
State Elements (registers) <= yn+1 = f(inputs, yn)
State elements are mixed in with CL blocks to control the flow of data.
EECS 150 Digital Design Lecture 5 Notes
Flip-Flop Timing Details
Three important times associated with flip-flops:
o setup time
o hold time
o clock-to-q delay
Always blocks are the only way to specify the behavior of state elements. Synthes
EECS 150 Digital Design Lecture 3 Notes
Schematic entry/editing used to be the standard method in industry and universities.
Used in EECS150 until 2002
Schematics are intuitive. They match our use of gate-level or block diagrams.
EECS 150 Digital Design Lecture 2 Notes
Integrated Circuit Example
PowerPC microprocessor micro-photograph
o Superscalar (3 instructions/cycle)
o 6 execution units (2 integer and 1 double precision IEEE floating point)
o 32 KByte Instruction and Data L1 c
CS150 Fall 2013 HW9 Solutions
Problem 1: Adders.
For each part, use 4 bit blocks, 2 input gates only. Estimate number of 2 input gates used (assume AND,
NAND, OR, NOR, and that inverters can be considered part of 2 input gates). Also est
EECS150/Problem Set 1 Solution
Due at 10 am, Thu. Sep. 12
Reading Harris and Harris: 1.1-1.6, 2.1-2.6, 4.1-4.3, 4.5, 4.8
1. (10 pts) Base Representation. Perform the following number system conversions (assume