Lab 9: Design of a Traffic Light Control
Post-Lab Deliverables
a)
1) Binary Encoding2) Ones Hot Encoding3) Johnsons Encoding4) Grey Codeattatched
b)
c) Of the two styles of machines, I believe the Mealy Machine is better. It allows you to
design a circuit
Lab 9: Design of a Traffic Light Control
Pre-Lab Deliverables:
a) In order to implement my design I used a Mealy machine. I did this because my TLC
depended not only on the state it was in, but also required input from pedestrians and
cars. (Diagram on la
Lab 8: 16-bit ALU with eight operations
Objectives:
The objective of this lab was to create an Arithmetic Logic Unit that performs 8 different
operations. We receive input of two, 16 bit numbers and output a 32 bit result. We use the
XILINX FPGA to implem
Lab 7: Carry Look Ahead and Carry Save Adders
Objectives:
The objective of this lab is to design two different types of adders and implement them on the
XILINX FPGA. The first design calls for us to use carry look ahead adders to add two 16 bit
numbers. T
AndrewZeller
Lab 6
AndrewZeller
Objectives:
The objective of this lab is to design an eight bit counter that interacts with the XILINX FPGA.
Through this design we will learn to implement several different De-Bouncing techniques and
control the LCD displa
Lab 6: De-Bouncing, Counters & LCD Display Control
Pre-Lab Deliverables
a) The calculated average number of bounces for Design 2 was, in decimal, 49. For
Design 3 the average number was 43, in decimal. This makes sense because the rotation
knob was easier
Lab 5: Xilinx Ripple Adder
Pre-Lab Deliverables
a)
b)
`timescale 1ns / 1ps
module FA(a,b,sum,carry);
input [7:0] a, b;
output [7:0] sum;
output carry;
/wire ab,ca,bc;
reg [7:0] sum;
reg carry;
always@ (a or b)
begin
cfw_carry=a+b;
end
/xor(S,A,B,Cin);
/an
Andrew Zeller
June 22, 2011
Lab 4: Multiplexer Based Arithmetic Logic Unit
Andrew Zeller
June 22, 2011
Objectives:
The objective of lab 4 was to design a basic four bit ALU using a
multiplexer to control the operations. The ALU does basic computations
suc
Lab 3: Study and Implementation of Adders
Objectives:
The objective of this lab is to become familiar in the use and implementation of
half adders and full adders. Using a combination of full adders, we will construct
an n-bit ripple carry adder. We will
Lab 2: Logic Minimization and Karnaugh Maps
Objectives:
The objective of this experiment is to use logic minimization techniques to apply digital
electronics to real life scenarios. The main minimization technique we will be learning is
the Karnaugh Mao.
Lab 8: 16 Bit ALU with eight operations
Post-Lab Deliverables
a)
i) The given circuit has an output of 1 if the input IN is equal to one, but only for the
period from the instant it is 1 until time T1+T2.
ii) attatched
iii) For the Duty cycle to be 50%, t