Lab 6: Introduction to Logic Simulation and Verilog
Date: October 16, 2013
Objective
This lab was an introduction to using the Verilog hardware description language. The design aspect
of the lab manual was minimal, since the purpose was to simply apply ne
Lab 3: Logic Minimization with Karnaugh Maps
Date: September 25, 2013
Objective
The lab was conducted to teach students how to use Karnaugh maps for logic minimization. It
also tests a pre-designed profit calculator using a seven segment display to see ho
Lab 4: Rudimentary Adder Circuits
Mark Franklin
ECEN 248-509
TA: Edward He Hao
Date: 2/11/2013
Due: 2/18/2013
Objectives:
This lab focused on the particular topic of adder circuits. These adder circuits were
beneficial in that they are a simple way to dem
Lab 6: Introduction to Logic
Simulation and Verilog
Rebecca Sontheimer
ECEN 248-511
TA: Mehanz Rahman
Date: October 22, 2013
Objectives
The purpose of this lab was to introduce Verilog programming. Verilog programming is
an alternative to breadboarding wh
Lab 3: Logic Minimization with
Karnaugh Maps
Mark Franklin
ECEN 248-509
TA: Edward He Hao
Date: 2/4/2013
Due: 2/11/2013
Objectives:
This lab was effective introduction into the practical uses of circuits. It tested the design
skills of the students by req
Below is the code simulated for the combination_lock_fsm.v :
`timescale 1ns/ 1ps
`default_nettype none
/*This module describes the combination-lock *
*FSM discussed in the prelab using behavioral *
*Verilog */
module combination_lock_fsm(
/*for ease of de
Midterm 1 ECEN 248 (Fall 2013)
Sign the following statement:
On my honor, as an Aggie, I have neither given nor received unauthorized aid on this academic
work
Name:
1.Number base conversions(10pt)
(i)[5pt] Convert (101011.01)2 into base 16;
(ii)[5pt] Con
Lab 8: Introduction to Sequential Logic
Date: October 30, 2013
Objective
This lab was conducted to familiarize the students with the concept of sequential logic circuits and
elements such as latches and flip-flops. Verilog will be used to describe and sim
ECEN 248
Exam 2 Fall 2015
Name:
Score:
1. (10 points) Given a clock that runs at 100 MHz, slow it down to 20 MHz. You
are allowed to use adders, shifters, or a counter. No other gates are allowed.
2. (15 points) Use T ﬂip-ﬂops to build a 3-bit synchronous
Lab 3: Logic Minimization with
Karnaugh Maps
ECEN 248 507
TA: Yuhan Zhou
Date: February 22, 2015
1. Objectives:
In this lab, I learned about practical uses of circuits by Karnaugh Maps and truth tables. First
of all, I able to create a truth table and des
Lab 5: Simple Arithmetic Logic Unit
Mark Franklin
ECEN 248-509
TA: Edward He Hao
Date: 2/18/2013
Due: 2/25/2013
Objectives:
This lab was an opportunity to apply and gain deeper understanding of a number of
different things in the current curriculum: First
Lab 3: Logic
Minimization with
Karnaugh Maps
Deanna Sessions
ECEN 248- 511
TA: Priya Venkatas
Date: September 24, 2013
Objectives:
The objective of this lab is to be able to simplify a calculator circuit by the usage of Karnaugh
Maps and truth tables. Thi
RebeccaSontheimer
ECEN248511
Prelab:Lab5
1. ExamplesdemonstratinghowthecircuitinFigure5addsandsubtractsandhow
theoverflowdetectioncircuitworks.
2. TruthtableandminimizedBooleanexpressionfora1bitwide,2:1multiplexer.
Truth Table for 2:1 Multiplexor:
S
A
B
F
ECEN 248
Exam 1
Spring 2011
Exam time: 9:45 am to 10:45 am, February 15, 2011
Instructor: Prof. Weiping Shi, wshi@ece.tamu.edu
Name: _ Score: _
1. (5 points) Match the name and the invention by drawing a line between the name
and the invention. If you can
Dept. of Electrical and Computer Engineering
TAMU
Lab 1: Introduction to Combinational Design
PART I
Study of Standard Gates
1.1 Introduction
The purpose of this experiment is to introduce you to the basics of circuit wiring,
troubleshooting, logic interp
Lab 7: Introduction to Behavioral Verilog
and Logic Synthesis
Date: October 16, 2013
1. Verilog code with comments for the 2:4 binary decoder, the 4:2 binary encoder, and the
4:2 priority encoder. Do not use behavioral Verilog for these descriptions! Use
Lab 1: Digital Logic Gates
Mark Franklin
ECEN 248-509
TA: He Hao
Date: January 28, 2013
Objectives:
The primary purpose of this first lab was to give us some hands-on knowledge of some of
the logic gates that weve only seen on paper up to this point. Thou
Rebecca Sontheimer
ECEN 248-511
Homework 5
3.2 Compute the clock period for the following clock frequencies.
A. A. 32.768 kHz
1/32768 = 30.5 us
B. 100 MHz
1/100,000,000 = 10 ns
C. 1.5 GHz
1/1,500,000,000 = 0.66 ns = 667 ps
D. 2.4 GHz
1/ 2,400,000,000 = 0.
Lab 3: Adders
Derek W. Johnson
ECEN 248-506 Aaron Hill February 15, 2008
Objectives
This lab aims to increase the student's understanding of ripple carry adders, and teach the student how to design multiple bit adders by combining single bit adders
Lab 5: 8-bit Counters
Derek W. Johnson
ECEN 248-506 Aaron Hill February 29, 2008
Objectives
This lab will increase the student's understanding of counters and clocks. The lab will explore the differences between a debounced clock and a non-debounce
Lab 3: Logic Minimization
with Karnaugh Maps
Rebecca Sontheimer
ECEN 248-511
TA: Mehnaz Rahman
September 25, 2014
Objectives:
The purpose of this lab is to design a profit calculator using various integrated
circuits, a breadboard, seven-segment display,
ECEN 248: INTRODUCTION TO DIGITAL DESIGN
Lecture Set A Dr. S.G.Choi Dept. of Electrical and Computer Engineering
Instructor:
Office 333G WERC Office Hours MWF 10-11 AM Email: gchoi@ece.tamu.edu
Lab Page: http:/ people.tamu.edu/~rajballavdash/e
2015/1/28
ECEN 248: INTRODUCTION TO
DIGITAL SYSTEMS DESIGN
Lecture 4
Dr. Weiping Shi
Dept. of Electrical and Computer Engineering
KARNAUGH MAPS
1
2015/1/28
Overview
K-maps: an alternate approach to represent Boolean
functions
K-map representation can be u
2015/1/22
ECEN 248: INTRODUCTION TO
DIGITAL SYSTEMS DESIGN
Lecture 1
Dr. Peter Weiping Shi
Dept. of Electrical and Computer Engineering
Instructor:
Dr. Peter Weiping Shi
Office 333K WERC
Office Hour: MWF 10:00-12:00 pm
Email: wshi@ece.tamu.edu
Phone: 979-
ECEN 248: INTRODUCTION TO
DIGITAL SYSTEMS DESIGN
February 13, 2015
Dr. Weiping Shi
Dept. of Electrical and Computer Engineering
Examples
3-Input Look Up Table (LUT)
A
8-to-1 MUX with three select lines
0
0
0
0
0
0
0
1
This LUT
implements a 3inp
Sequential Circuits
Models for representing sequential circuits
Finite-state machines (Moore and Mealy)
Representation of memory (states)
Changes in state (transitions)
Design procedure
State diagrams
Implementation choice: counters, shift registers,
ECEN 248: INTRODUCTION TO
DIGITAL SYSTEMS DESIGN
Week 3
Dr. Srinivas Shakkottai
Dept. of Electrical and Computer Engineering
KARNAUGH MAPS
Overview
K-maps: an alternate approach to representing
Boolean functions
K-map representation can be used to minimi
ECEN 248: INTRODUCTION TO
DIGITAL SYSTEMS DESIGN
Week 7
Dr. Srinivas Shakkottai
Dept. of Electrical and Computer Engineering
SEQUENTIAL CIRCUITS: LATCHES
Overview
Circuits require memory to store intermediate data
Sequential circuits use a periodic signa