ECE 3311002
Exam 1 Review
Exam Info
Date: March 6th
Regular class time and class location
You may bring a 3x5 notecard with formulas
Calculator is permitted
There will be 1 bonus question
Study the Homework!
Solutions for Homework 1 & 2 are on Blac
5
D
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2
1
In these problems, you have the following components:
BSS127 nchannel MOSFETs.
Resistors.
Capacitors (including CCs).
Inductors (including RFCs).
One positive battery with your choice of voltages.
One negative battery with your choice of volt
You will be doing 4 design problems. You get to work with
inductors
capacitors
resistors
transformers
ideal op amps that can drive 1K loads to the rails (they still dont take inputs at or outside the rails)
ideal comparators that drive to the rails (they
5
4
3
2
1
Using IRF5NJ6215 transistor(s) and diodes (no opamps allowed), design a
circuit that will output
(V1 AND V2) NAND (V3 NOR V4)
V1, V2, V3, V4 are 5V logic.
The load is 50 Ohms.
D
D
V1
C
V2
C
VOUT
Rload
50
B
B
V3
V4
A
A
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1
5
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1
What i
You will be doing 2 design problems and 2 analysis problems. You get to work with
inductors (including RFCs)
capacitors (including CCs)
resistors (up to 1 Watt)
transformers
ideal PN diodes with a forward drop of 0.7V
ideal Zener diodes with whatever reve
5
4
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2
1
3. Vin is a small signal in the +/ .01 V range. Find the DC bias for all nodes in the circuit. Find Id and gm for all transistors. Find Vout. Do any of the transistors break?
Is the output wave distorted?
D
D
24V
RS
5K
24V
24V
C
1
C
100K
24V
Q2
5
D
4
3
2
1
In these problems, you have the following ideal components:
Resistors.
Capacitors.
Inductors.
Rail to Rail op amps that cannot accept inputs outside the rails.
Standard comparators that drive to top rail for TRUE and drive to bottom rail for F
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4
3
2
1
20V
D
D
1 mA
V1 + 1.1V
.109 ~= .1 mA
RB1
4K
.4V drop
Q1
NPN BCE
RB2
7K
.9 mA
1
.7V / 7000 = .1 mA
.009 mA
C
 1.1V drop +
Vout
C
2
V1
20V
B
B
A
A
Title
<Title>
Size
A
Date:
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Document Number
<Doc>
Friday, June 27, 2014
2
Rev
<RevCode
Sheet
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Current out for voltage in
ID = Beta/2 * (Vgs  Vt) ^ 2
Gm = 2 ID / (Vgs  Vt) = Beta (Vgs  Vt)
D
Gm = sqrt (2 Beta
* ID)
D
Gm = Gmr sqrt (ID / IDr)
Input impedance is pure capactive
r0 * ID = Early Voltage = r0r IDr
capacitor from GD, GS, D
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4
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2
1
VCC
VCC
RD
1K
3
RG1
D
RSIG
gain = gm RD / (1 + gm RS)
D
CC
1
1
gain = + gm RS / (1 + gm RS)
2
VSIG
RS
1K
2
RG2
If RS = RD, outputs produce both
plus and minus with same magnitude.
C
C
B
B
A
A
Title
<Title>
Size
A
Date:
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Document Number
<Do
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It is common but not universal to show the minus terminal on top
We'll use the superposition trick to make life easier.
R1
D
D
Vplus
2
1
Vi2
V+ 3
1
R3
V1
Vout
+
V 4

1
R2
Vi1
5
U1
R4
Vminus
2
2
V2
C
C
To consider Vi1, Set Vi2 to 0. Inverting a
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1
R1
What is V3(s), assuming an ideal op amp?
ZC = 1 / (s C)
R2
1
V1
D
+5V
D
V1
1
11
V2
2
1
V2
3
400K
2
4
+5V
V3
+
2
U1A

C
600K
5V
C
C
5V
B
B
A
A
Title
<Title>
Size
A
Date:
5
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Document Number
<Doc>
Thursday, May 24, 2012
2
Rev
Sheet
1
of
1
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VSIG is a rapidly varying AC signal in the +/ 1 mV range. Identify all transistor bias values. What is Vout?
D
D
20V
20V
RLOAD
5K
1Meg
RSIG
Vout
CC
Q4
1
1K
Input voltage divider
VSIG
C
1 mV
C
2
20V
VB
VE
VC
IB
IE
IC
gain
gm
rpi
rin
rload
10K
Assume room temperature for all devices.
Explain where you get your numbers for transistor bias solutions.
Dont panic at the use of PNP and NPN transistors.
You will be doing 2 design problems and 2 analysis problems. You get to work with
inductors (inclu
(This is based on problem 7.126, which I worked in class.)
Design (draw the circuit and find the component values) a commonemitter amplifier with the following
requirements:
Amplifier should operate between a 2k signal source and a 2k load
Amplifier sh
Small Signal Analysis of a PMOS transistor
Consider the following PMOS transistor to be in
saturation. Then,
1
ISD = pCox(VSG Vtp )^ 2(1 + VSD )
2
From this equation it is evident that ISD is a function of
VSG, VSD, and VSB, where VSB appears due to the t
MOSFET Amplifier Configurations
(7.3)
Spring 2017
ECE 3311002
References:
Microelectronic Circuits by Sedra/Smith
Basic MOSFET Amplifier Configurations (7.3.1)
There are 3 basic configurations for using a MOSFET as an
amplifier.
In each configuration,
BJT Biasing (7.4)
Spring 2017
ECE 3311002
References:
Microelectronic Circuits by Sedra/Smith
BJT Biasing Cases (7.4.2)
Classical BJT DiscreteCircuit Bias Arrangement
Figure 7.52 Classical biasing for BJTs using a single power supply: (a) circuit; (b) c
Using the BSS806N NMOS transistor, the theoretical BSS806P PMOS transistor (which is a perfect complement to
the NMOS), Rs, CCs, RFCs, no more than 1 positive battery, and no more than one negative battery, design a
circuit to do the following. Dont break
V1 is an analog signal between +/ 1 V. We are interested in its derivative, d V1 / dt. A slow change in V1
should result in a circuit that outputs V1. A rapid change in V1 should result in a circuit with 0 output.
Design a circuit to output Vout as follo