Laboratory I: TTL Characteristics Performed by Due September 24, 2007
Goals of the Lab (1) To study TTL voltage characteristics and their implications for analysis and design. (2) To familiarize the student with the TTL databook. (3) To implement th
Question 1
2 out of 2 points
Which of the following statements about protein is NOT correct?
Selected Answer: Protein is made up of 20 essential amino acids
Question 2
2 out of 2 points
Vaness has a body fat percentage of 25, which falls into the healthy
ECE 3W! $:>r\'vg 20:6 muzxw . 3mm
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CULLEN COLLEGE OF ENGINEERING
N DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
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The Digital Design Process and Introduction to Computer
Aided Design II
Aldo Vela
Daniella Olakpe
03/02/2016
Lab 3
Introduction
The objective of lab 3 was to use what we learned from our previous lab experiment to
physically build a logical expression. Th
Assignment 1
Creating a Resume in Microsoft Word
For this assignment you must create a resume in Microsoft Word. During this process
you should learn the basics of formatting a Word document. The grading rubric is as
follows:

20%  Presentation
40%  Co
Page 1 of 1
ECE 3331 Test 1, Spring 2015 solutions
Problem 1. 2
Problem 2. (c) compile error (we did this example in lecture)
Problem 3. 2*2+3=7
Problem 4. (C) * / % +  =
Problem 5. (B) 5, 6, 7, 8
Problem 6 (d) result = 2 8%3;
Problem 7.
fin=fopen("c:fil
ECE 4436 Sample Final Exam Spring 2011
Closed book and notes No calculators or computers
Instructorspecified handouts are allowed
SHOW ALL WORK!
You have a UART (Universal Asynchronous ReceiverTransmitter) that you need to interface to
the MC9S12C32. Th
ECE 3436 Spring 2016 Lab # _2_
Partner Evaluation Form
Your Name: _Daniella Olakpe_
STATEMENTS
Partner Name: Charles Asquith
RESPONSE
My Partner contributed to the team.
On this lab I feel that during the
code writing portion my partner
did/did not contri
Introduction to African American Studies (AAS 2320)
Fall 2014
Tuesdays & Thursdays, 1:00 pm2:30 pm
Instructor:
Office:
Office Hours:
Phone:
Email:
Malachi D. Crawford, Ph.D.
Agnes Arnold Hall 634;
Tue., Thur. 9:00 a.m. 10:00 a.m., and by appointment.
71
Name: Daniella Olakpe
Rewrite the following sentences to make them more concise and precise. From Philip Laplante,
Technical Writing: A Practical Guide for Engineers and Scientists
1. The mechanism will require a substantial amount of redesign.
The mechan
#include <iostream>
#include <math.h>
using namespace std;
int main()
cfw_
int m, n;
int go ;
cout < "Do you want to continue?" < endl;
cout < "Enter 1 for yes 0 for no: ";
cin >go ;
while (go=0) cfw_
exit(1);
cout < "Enter positive integers for m and n:
ECE 3441
Digital Logic Design
Syllabus and Course Information
Instructor:
Dr. Haluk Ogmen
Office: W312 Engineering Building 2
Phone #: 713 7434428
Email: ogmen@uh.edu
FAX #: (713) 7434444
Office Hours: Will be announced in class and posted on the Black
Logic Functions & Gates + Boolean Theorems + Karnaugh Map
v1.00
5/18/2004
Logic Functions & Gates
Logic Gate
NOT
AND
OR
NAND
NOR
XOR
XNOR
Y = 1 if A OR B = 1
Y = 0 if A AND B = 1
Y = 0 if A OR B = 1
Y = 1 if A OR B = 1, not if both = 1
Y = 0 if A OR B = 1
111907 ECE 3441 Homework #10 12.12 a)
b) Q3+=ld'sh'Q3+ ld sh'D3+sh Q2 Q1+=ld'sh'Q1+ ld sh'D1+sh Q0
Q2+=ld'sh'Q2+ ld sh'D2+sh Q1 Q0+=ld'sh'Q0+ ld sh'D0+sh SI
12.13
12.17 a) DA=B C D + A D' DC=A' C' D + C D' b) JA=B C D KA=D c) SA=B C D RA=C' D
Laboratory III: The Digital Design Process and Introduction to Computer Aided Design II Performed by Due October 12, 2007
Goals of the Lab (1) To become familiar with LogicAid. (2) To become familiar with SimUaid. (3) To implement LogicAid in order
ECE 3441 Laboratory IV: Modular Design and Hierarchy Performed by Due October 26, 2007
Goals of the Lab (1) To become more familiar with SimUaid. (2) To test and implement the "Full Adder" Circuit in SimUaid. (2) To test the operation of the macroc
ECE 3441 Laboratory V: Hardware Implementation of a 4Bit Adder Performed by Due November 2, 2007
Goals of the Lab (1) To become more familiar with LogicAid. (2) To become more familiar with SimUaid. (3) To design a 4bit binary adder and subtractor
ECE 3441 Laboratory VI: Arithmetic Circuits using 4bit adder IC Performed by Due November 9, 2007
Goals of the Lab (1) To understand the IC 74LS83 4bit adder. (2) To design an arithmetic circuit using the 4bit adder IC 74LS83. (3) To build and te
ECE 3441 Laboratory VIII: Design of a Traffic Controller Performed by Due November 30, 2007
Introduction One goal of this lab is to design a traffic controller using flipflops and logical gates. Another goal is to test its operation by applying a c
ECE 3441 Laboratory IX: Hardware Implementation of a Traffic Controller Performed by Due November 30, 2007
Introduction One goal of this lab is to implement our design of a traffic controller using JK flipflops and logical gates. We will also test
11507 ECE 3441 Homework #8 8.8 A=Z, B=0, C=X, D=Z, O=0, E=Z, F=X+0+0=X, G=(0Z)'=1, H=(X+1)'=0 8.9 For A=B=C=1, F(A,B,C)=(A+B'+C')(A'+B+C')(A'+B'+C)=1 In the figure, F=0 so there is something wrong with the circuit. Since the inputs to the last NOR
ECE 3441 Digital Logic Design
General Information about the Lab Assignments
A subset of the lab assignments involve hardware projects and will be carried out
in the Electronics Laboratory located in room S383D. The lab will be open during hours
posted in