Design for Test
Adapted from the work of M Nourani to whom I am grateful
1
Scan Design for Testability
2
Architectural View
A sequential circuit is
viewed as
A combinational logic
block, with
Primary inputs x1, x2, , xn
Primary outputs z1, z2, , zm
St
EE/CE 6301: Advanced Digital Logic
Bill Swartz
Dept. of EE
Univ. of Texas at Dallas
1
Scheduling
Synthesis and Design Automation
2
Architectural Synthesis
3
Synthesis
Transform behavioral into structural view.
Architectural-level synthesis
Architectural
EE/CE 6301: Advanced Digital Logic
Bill Swartz
Dept. of EE
Univ. of Texas at Dallas
EEDG/CE6301 B. Swartz
1
Testing
Testing of Digital Systems
2
VLSI Test Philosophy
3
Testing
Source: IEEE Spectrum
4
Test Philosophy
A Pass/Fail test:
Measurement probabil
EE/CE 6301: Advanced Digital Logic
Bill Swartz
Dept. of EE
Univ. of Texas at Dallas
1
Session 14
Graphs & Algorithms
2
Graph Theory - Background
3
Importance
Many optimization problems employ graph
representations to model the core part.
Graph theory ha
Relative Timing Driven Multi-Synchronous
Design: Enabling Order-of-Magnitude
Energy Reduction
Kenneth S. Stevens
University of Utah
Granite Mountain Technologies
27 March 2013
UofU and GMT
1
Learn from Prof. Kajitana
G
Think differently and deeply
G
Apply
EE/CE 6301: Advanced Digital Logic
Bill Swartz
Dept. of EE
Univ. of Texas at Dallas
EEDG/CE6301 B. Swartz
1
Session 10
Asynchronous Design
Adapted from the work of M Nourani to whom I am grateful
2
Optimization Techniques
3
State Minimization Implication
EE/CE 6301: Advanced Digital Logic
Bill Swartz
Dept. of EE
Univ. of Texas at Dallas
EEDG/CE6301 B. Swartz
1
Session 07
Multi-Level Optimization
Adapted from the work of M Nourani to whom I am grateful
2
Motivation for
Multi-Level Optimization
3
General Fo
FPGA Synthesis
Agenda
Brief tour in RTL synthesis
Basic concepts and representations
LUT-based technology mapping
The chortle algorithm
The FlowMap approach
2
RTL Representation
A structured system:
Made upon a set of combinational
parts separated by
Simulation of VHDL code with Synopsys Tools:
1- Connect to engnx server by using NX client or you can use Xmanager .
2- In order to set up the environment for running synopsys tools , use this command:
source /home/cad/Syn/bin/synopsys.profile
3- Let us s
THE UNIVERSITY OF TEXAS at DALLAS
DEPARTMENT OF ELECTRICAL
AND COMPUTER ENGINEERING
CE/EE 6301 Assignment # 2 Fall 2014
Question 1:
Given the function:
z = mp + mq + nop + t
Calculate the quotient and remainder using weak division if the divisor is
(a) x
THE UNIVERSITY OF TEXAS at DALLAS
DEPARTMENT OF ELECTRICAL
AND COMPUTER ENGINEERING
CE/EE 6301 Assignment # 1 Spring 2013
Question 1:
Given the function:
z = mp + mq + nop + t
Calculate the quotient and remainder using weak division if the divisor is
(a)
EE 6301: Advanced Digital Logic
When you submit your homeworks, to help us grade and identify your work, you need to comply
with the following guidelines carefully:
• Have a cover page for your homework and write clearly: (1) your name as it appears in yo