What is Verilog?
Verilog is a computer programming language used to model and simulate hardware designs. It is a
Hardware Description Language (HDL). Like C, it has if/else state
ECE 2700 Lab 3: Decoders and MUXes
Due at the end of your registered lab session (110 points)
Structure and application of N-to-2N decoders
Using decoders to encode truth tables
Using decoders to build larger decoders
ECE 2700 Lab 1
Due at the end of your registered lab session (70 points)
Become familiar with Xilinx ISE
Introduce behavioral programming in Verilog
Perform testbench simulation to verify design function
Deploy simple designs on the FPGA bo
ECE 2700 Lab 2: Combinational Logic and
Seven Segment Displays
Due at the end of your registered lab session (90 points)
Design using truth tables and combinational logic.
Derive efficient Boolean expressions from Truth Tables.
Design and ve
ECE Tutorial Linux Terminal Commands
Linux Tutorial Assignment
To learn basic terminal command skills in Linux and Unix environments.
Before doing these exercises, please study the Linux Tutorial available on the US
Steps to Making Lab Assignments Simple:
Do the pre-lab assignment. In addition to being graded at the start of your lab section, it will
prepare you well for the lab, saving you time in lab.
ECE 2700 Homework 5
Due Wednesday October 14, 2015 at the beginning of class (110 points)
Unless specified otherwise, all problems are from the main textbook (Digital Design with RTL Design,
VHDL, and Verilog). Late work and work that does not follow the
ECE 2700 Homework 4
Due Wednesday October 7, 2015 at the beginning of class (150 points)
All problems are from the main textbook (Digital Design with RTL Design, VHDL, and Verilog). Late
work and work that does not follow the required homework format will