EGR 234 Digital Logic Design
Lab 5 Hex-to-Seven-Segment Decoder Design Using VHDL
California Baptist University
Fall Semester 2014
Number of Lab Periods: 1
Due: Friday, October 17, 2014
1 Objectives
In this lab, you will learn how to design, simulate, and

EGR 234 Digital Logic Design
Lab 8 Arithmetic and Logic Unit Design Using VHDL
California Baptist University
Fall Semester 2014
Number of Lab Periods: 1
Due: Friday, November 7, 2014
1 Objectives
In this lab, you will design, simulate, and implement the A

EGR 234 Digital Logic Design
Lab 4 Digital Logic Circuit Design Using the DE2-115 Board
California Baptist University
Fall Semester 2014
Number of Lab Periods: 1
Due: Friday, October 10, 2014
1 Objectives
In this lab, you will be given a general overview

Syllabus
EGR 234 Digital Logic Design (4 units)
Instructor:
Textbook:
No text. Notes on topics covered in lectures will be supplied to the students.
Course Description (from CBU University Catalog):
Digital Logic Design (4). Boolean algebra, number system

EGR 234 Digital Logic Design
Lab 2 Binary Arithmetic
California Baptist University
Fall Semester 2014
Number of Lab Periods: 1
Due: Friday, September 19, 2014
1 Objectives
In this lab, you will learn how to use the Altera Quartus II design software. You w

EGR 234 Digital Logic Design
Lab 9 Adder/Subtractor Design with Signed Number Display
California Baptist University
Fall Semester 2014
Number of Lab Periods: 1
Due: Friday, November 14, 2014
1 Objectives
In this lab, you will first develop logic circuits

EGR 234 Digital Logic Design
Lab 6 Modular Approach for Adder Implementation
California Baptist University
Fall Semester 2014
Number of Lab Periods: 1
Due: Friday, October 24, 2014
1 Objectives
In this lab, you will learn how to design, simulate, and impl

EGR 234 Digital Logic Design
Lab 7 Double-Digit BCD Adder
California Baptist University
Fall Semester 2014
Number of Lab Periods: 1
Due: Friday, October 31, 2014
1 Objectives
In this lab, you will first build a 4-bit comparator, a 4-bit 2-to-1 MUX, and a

EGR 234 Digital Logic Design
Lab 10 Basic Memory Elements
California Baptist University
Fall Semester 2014
Number of Lab Periods: 1
Due: Friday, November 21, 2014
1 Objectives
In this lab, you will develop two basic memory elements - namely, gated D latch

EGR 234 Digital Logic Design
Lab 3 Design of a Simple Logic Circuit for a Car Ignition Problem
California Baptist University
Fall Semester 2014
Number of Lab Periods: 1
Due: Friday, October 3, 2014
1 Objectives
In this lab, you will go through the process

EGR 234 Digital Logic Design
Lab 11 Digital Clock Using Counters and VHDL
California Baptist University
Fall Semester 2014
Number of Lab Periods: 1
Due: Friday, December 5, 2014
1 Objectives
In this lab, you will design and implement a digital clock using

EGR 234 Digital Logic Design
Homework 9
California Baptist University
Fall Semester 2014
Due: Monday, December 1, 2014
Please carefully show your work leading to the nal answer.
1. (Timing Diagram for a Shift Register) Consider the following serial in/ser

EGR 234 Digital Logic Design
Lab 1: Implementation of Simple Logic Functions Using
Fixed-Function IC Gates
California Baptist University
Fall Semester 2014
Number of Lab Periods: 1
Due: Friday, September 12, 2014
1
Objectives
In this lab, we will go throu

USB-Blaster Driver for Windows Vista
Home > Support > Downloads > Cable & Adapter Drivers > USB-Blaster Driver for Windows Vista
You must install the Altera USB-BlasterTM download cable driver before you can use it to program devices
with Quartus II softw

EGR 234 Digital Logic Design
Homework 3
California Baptist University
Fall Semester 2014
Due: Wednesday, October 1, 2014
Please show all your work leading to the nal answer.
1. (Truth Table Standard POS Form) For each of the following truth tables, derive

Altera software download
Go to:
https:/www.altera.com/download/sw/dnl-sw-index.jsp
then under Software Selector, choose tab Select by Version and then choose
Quartus II Software, Version 13.0, Service Pack 1, be sure to download the Web Edition (as this d

EGR 234 Digital Logic Design
Homework 7
California Baptist University
Fall Semester 2014
Due: Wednesday, November 5, 2014
Please carefully show all your work leading to the nal answer.
1. (A Disk Position Decoder Using Gray-Binary Code Converter And 3-to-

#=
# Build by Altera University Program
#=
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE115F29C8
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignme

EGR 234 Digital Logic Design
Homework 5
California Baptist University
Fall Semester 2014
Due: Monday, October 20, 2014
Please carefully show all your work leading to the nal answer.
1. (SOPmin and POSmin Expressions) Determine the SOPmin and POSmin expres

EGR 234 Digital Logic Design
Homework 8
California Baptist University
Fall Semester 2014
Due: Friday, November 14, 2014
Please carefully show your work leading to the nal answer.
1. (Characteristic Table for Cross-Coupled NAND Gates) Determine the charact

EGR 234 Digital Logic Design
Homework 6
California Baptist University
Fall Semester 2014
Due: Wednesday, October 29, 2014
Please carefully show all your work leading to the nal answer.
1. (Modular Approach for Algorithmic Statements) A circuit has two 8-b

EGR 234 Digital Logic Design
Homework 1
California Baptist University
Fall Semester 2014
Due: Wednesday, September 17, 2014
Please carefully show all your work leading to the nal answer.
1. (Binary Decimal) Convert the following binary numbers to decimal.

EGR 234 Digital Logic Design
Homework 4
California Baptist University
Fall Semester 2014
Due: Monday, October 13, 2014
Please carefully show all your work leading to the nal answer.
1. (Simplication of Logic Expressions) Simplify the following logic expre

EGR 234 Digital Logic Design
California Baptist University
Fall Semester 2014
Some Basic Memory Elements
In this supplementary reading, we will show some basic memory elements. In particular, we will pay
attention to their circuits, graphical symbols, cha

EGR 234 Digital Logic Design
Fall Semester 2014
Symbolic State Minimization and An Example
Symbolic State Minimization
In constructing state diagrams, it often occurs that the number of symbolic states that we use is not the
minimum possible to perform th

EGR 234 Digital Logic Design
Homework 2
California Baptist University
Fall Semester 2014
Due: Wednesday, September 24, 2014
Please carefully show all your work leading to the nal answer.
1. (Symbol Truth Table) Determine the truth table for the three-inpu

EGR 234 Digital Logic Design
California Baptist University
Fall Semester 2014
Counters with T Flip-Flops
Counters can be implemented using the adder/subtractor circuits and registers (or equivalently, D ipops) as discussed in the text (such counters are t

EGR 234 Digital Logic Design
California Baptist University
Fall Semester 2014
Some Discussion on Basic SR Latch
Let us consider a basic SR latch built with NOR gates as shown in Figure 1. The signals Qa and Qb
describe the state of this memory element.
R

EGR 234 Digital Logic Design
California Baptist University
Fall Semester 2014
Design of Multipliers for Unsigned Binary Numbers
Let us rst consider the the general task of multiplication. Two binary numbers can be multiplied using
the same method as we us

Chapter 2
The Binary Number System
In this chapter, we introduce the binary number system which is the number system
used in modern computer science. We begin by considering nonnegative numbers which
can be expressed using positional number representation