Intro to Digital Logic, Lab 4
HighLevel Verilog
Lab Objectives
Implementing designs directly in schematics or structural (gatelevel) Verilog can give you
the best control, and often the smallest designs. But, sometimes it can be a real pain to
optimize
EE271
Review Problem 0
As you wait for class to start, answer the following
question:
Bob has $500, but owes $300 to Shirley in CA, whos going
to kill him if he doesnt pay off the money in person in a
week. Plane tickets to CA cost $175, while bus tickets
Intro to Digital Logic, Lab 2
An Introduction to Verilog and Digital Components (Part 2)
Lab Objectives
In lab #1 you learned the basics of entering a design for simulation in Quartus II, and how to
wire up a basic gate on the breadboard. In this lab we w
Intro to Digital Logic, Lab 3
Digital Design using FPGAs
Lab Objectives
Now that you know how to develop Verilog designs and load them into the DE1 SoC board,
we can now start looking at more complex designs.
Design Problem Multilevel logic on the DE1 F
Intro to Digital Logic, Lab 5
Sequential Logic
Lab Objectives
Now that we have mastered combinational logic, it is time to figure out sequential circuits.
In this lab you will download a premade design to your board. Then, you get to design your
own circu
Intro to Digital Logic, Lab 6
Communicating Sequential Logic
Lab Objectives
In the last lab we developed a single, simple FSM. Now we want to build a more complex
system with multiple FSMs. Careful creation of a block diagram, and design and testing of
ea
Finite State Machines
Readings: 66.4.7
Need to implement circuits that remember history
Traffic Light controller, Sequence Lock, .
History will be held in flip flops
Sequential Logic needs more complex design steps
State Diagram to describe behavior
Stat
Intro to Digital Logic, Lab 8
Final Project
Lab Objectives
Now that you are an expert logic designer, its time to prove yourself. You have until about
the end of the quarter to do something cool with the DE1 board and your digital design skills.
Note that
Intro to Digital Logic, Lab 7
Useful Components
Lab Objectives
Over the last 6 labs weve learned how to do most kinds of basic logic, but there are some
standard elements that tend to come up over and over again. This lab will help you get some
experience
Intro to Digital Logic, Lab 1
An Introduction to Verilog and Digital Components (Part 1)
Lab Objectives
Read the whole lab first before starting on any work. The first lab for EE 271 will introduce
you to the Alteras Terasic DE1SoC Development board and
CMOS Transistors
Readings: B.1B.3.1
All circuit elements built from transistors
conductor  gate
insulator
source
drain
gate
Ntype
drain
n
source
n
p
substrate
conductor  gate
insulator
source
drain
gate
drain
Ptype
p
source
p
substrate
n
214
Transis
Registers
Readings: 5.85.9.3
Storage unit. Can hold an nbit value
Composed of a group of n flipflops
Each
flipflop stores 1 bit of information
D
Q
Dff
clk
D
Q
Dff
clk
D
Q
Dff
clk
D
Q
Dff
clk
178
Controlled Register
Reset
0
1
0
Load
0
0
1
Action
Q =
Basic Circuit Elements
Readings: 44.1.1, 4.2, 4.34.3.2
Standard TTL SmallScale Integration:
1 chip = 28 gates
Requires
numerous chips to build interesting circuits
Alternative: Complex chips for standard functions
Single
chip that performs very com
EE 331 Devices and Circuits I
Problem Set #3
Autumn 2015
Problem #1
2.45
Problem #2
3.1
1018
1019
Problem #3
3.2
1016
Problem #4
3.6
Problem #5
3.21
5 1018 A
Problem #6
3.25
1.07
Problem #7
3.41
1018
EE 331 Devices and Circuits I
Problem Set #2
Autumn 2015
Problem #1
2.16
1800
700
You may have to solve an equation here numerically. If you are within 10 % of the
correct temperature, you have an acceptable answer.
Problem #2
2.21
Problem #3
2.23
180
Pro
Combinational Logic Design Process
1. Understand the Problem
what is the circuit supposed to do?
write down inputs (data, control) and outputs
draw block diagram or other picture
2. Formulate the Problem in terms of a truth table or other suitable
design
Combinational vs. Sequential Logic
Readings: 55.4.4
X1
X2 Xn 
Logic
Network

Z1
Z2
Network implemented from logic gates.
The presence of feedback
distinguishes between sequential
and combinational networks.
Zm
Combinational logic
no feedback among inpu
Optimization via KMaps to 2level forms
Readings: 2.112.12.2, 2.14
Sum of Products form: the OR of several AND
gates, inversions over only inputs
F = X+YZ+XYZ
Circuit diagram & inversions:
46
On Sets and Off Sets
X
0
0
0
0
1
1
1
1
Y
0
0
1
1
0
0
1
1
Z
0
Number Systems
Readings: 33.3.3, 3.3.5
Problem: Implement simple pocket calculator
Need: Display, adders & subtractors, inputs
Display: Seven segment displays
Inputs: Switches
Missing: Way to implement numbers in binary
Approach: From decimal to b
271: Introduction to Digital Circuits and Systems
Professor Scott Hauck, EEB307Q
([email protected])
Office Hours: stop by or email w/schedule for a slot
Book: Brown & Vranesic Fundamentals of Digital Logic
with Verilog Design (3rd Edition)
TAs (EE