10/8/2012
ECE 352
Digital System Fundamentals
Week 6
Carry-Lookahead Adders
ECE 352: Digital System Fundamentals
Fall 2012
This Week
Demo#2 @3650 lab
Written HW#3 due Wednesday 5PM
Read: 4.5, CLAs
W6
2
ECE 352: Digital System Fundamentals
Fall 2012
Top
Monday,October08,2012
9:20AM
Create a "multiply by 3" circuit that has 4-bit input A3:0 and outputs
the 6-bit product P5:0.
W6-M Page 1
Generate: Based on the
operand values at just this bit
position, will my carry-out for
this position be 1 regardless o
Friday,October05,2012
10:51AM
W5-F Page 1
W5-F Page 2
Worksheet: Contraction
Given a 3-bit adder, use contraction to create a decrement-by-2 circuit.
A
A
A
B
B
B
C
C
C
CIN
S
CIN
S
ECE/CS 352: Digital System Fundamentals
CIN
S
Friday,September21,2012
10:50AM
W3-F Page 1
W3-F Page 2
Worksheet: Prime Implicants
#1) Identify the prime implicants for the below K-Maps and identify those that are essential.
Prime Implicant
Prime Implicant
CD
AB
00
01
11
1
1
1
1
01
1
1
0
0
11
1
1
1
1
Monday,September17,2012
9:30AM
W3-M Page 1
Worksheet: Basic K-Maps
#1) Fill in and label the 3-variable K-Map based on the given Truth Table:
W
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
Y
0
1
0
1
0
1
0
1
Z
0
1
0
1
1
0
1
1
#2) Solve the following 3-variable K-Maps
Decoders
Decoders are a combinational circuit that allows us to take a binary input and translate it into an enable
signal. For a given input combination, only a single output will be active (1).
2-to-4 Decoder
3-to-8 using 3-input AND gates
3-to-8 Decode
Applied Homework 1
F12
APPLIED HOMEWORK #1
Logic Gate Properties &
Design Using FPGAs
1-1 DESCRIPTION AND HOMEWORK OBJECTIVES
This Applied Homework has two parts. The first part is a tutorial on the Quartus design tool . The bulk of this work is
part of t
Begin Replacing AND/OR Gates with their functional equivalents built out of NAND Gates.
Remember to show how to generate a NOT gate using a NAND so you can use the Inverter
in your circuit.
When Done, you can remove any redundant Inverters
10/1/2012
ECE 352
Digital System Fundamentals
Week 5
Common Combinational Structures
Implementing Digital Logic
Adders, Complements, Subtractors
ECE 352: Digital System Fundamentals
Fall 2012
This Week
Pre #2 Due W 10/3
Reading 4.1 4.5
W5
2
ECE 352: Dig
ECE/CS 352
Homework #3
Due 10-Oct-12 @ 5pm
(at the 3650EH dropbox)
Name
_
Student ID
_
[Partners Name]
_
Section (circle)
8:50AM
11:00AM
Please turn in your work on a printout of this document, giving your answer in boxes or on lines when given, and
showi
Carry Lookahead Adders
A Ripple Carry Adder (RCA) is a very area-efficient adder design. Unfortunately, it is also slow. The maximum delay of
an RCA is from the carry-in input (or the vector inputs at position 0 if there is not a carry-in input) to the ca