3.14 You have been hired by the MITDAC Corporation to write a
FIGURE 3.144 product description for a new 4-bit digital-to-analogconverter resistance ladder. Because of mask tolerances in VLSI chips,
each resistor shown in Figure 3.145 is guaranteed to be

not symmetric.) So its drain and source labels can be interchanged
without changing the device. Accordingly, if the drain and source
nomenclature was unrelated to the potential difference between the two
terminals, the MOSFET characteristic would look lik

independent statements of KCL needed to determine the unknown node
voltages can similarly be reduced by one. Thus, Nodes 1 and 2 in Figure
3.20 must together contribute one statement of KCL to the first part of
Step 3 of the node analysis (namely, writing

equivalent of the circuit in Figure 3.118 at the terminals indicated. v R1
R3 R2 v2 + - - + I v1 + - FIGURE 3.117 v R1 R3 R2 v + - I + - i
FIGURE 3.118 e x e r c i s e 3.18 In the circuit shown in Figure 3.119
there are five nodes, only three of which are

circuits 2. Find the incremental output voltage and incremental nonlinear
device current by forming an incremental subcircuit in which the
nonlinear device is replaced by a resistor of value rd, where rd = 1 df
(vD) dvD vD=VD , other linear resistances ar

systems as early as possible in the curriculum to excite and motivate
students (especially with laboratory experiments), with (b) the need for
providing students with enough of a toolchest to be able to analyze
interesting digital building blocks such as

output voltage waveform for the circuit in Figure 5.34c in response to
the input voltage waveforms shown in Figure 5.35. Assume that the
gates in the circuit obey the static discipline with VOH = 4 V, VIH = 3 V,
VOL = 1 V, and VIL = 2 V. 0 5 V 1 V 4 V 3 V

incremental resistance rd = 25 . Similarly, for ID = 1.45 A, rd = 0.017 .
Note: The incremental resistance in general is not the same as the
resistor Rd used in the piecewise linear model of WWW Figure 4.33c.
There we were trying for a fit over a large ra

input voltage at G impacts the behavior of the MOSFET at its D and S
terminals, the voltages or currents at its D and S terminals have no
impact on G. 2. Second, the infinite resistance seen at the gate (G
terminal) of a MOSFET makes it have no effect on

1. Its outputs are a function of its inputs alone. 2. It satisfies the static
discipline. Figure 5.14 shows several useful gate symbols. We have
already seen the gate-level representation of the AND function. The OR
gate performs the OR function of its in

applying some form of excitation to the device terminals and obtaining
the relationship between the values of i and v. One of the simplest inputs
we can apply is a current source providing a current itest, as illustrated
in Figure 2.61b. The figure also s

a bit) represents one of two values (0, 1). Bigger numbers are
constructed by concatenating multiple digits. The multiple-digit decimal
number ijk formed by concatenating the decimal digits i, j, and k, has the
value i 102 + j 101 + k 100. Similarly, the

Equation 4.46 applies. Therefore vD = IR2 = 0.001 10000 = 10 V.
Let us now determine vD for the cosine current input depicted in Figure
4.27a. When I 0, vD = I R1 = I 100 as shown in Figure 4.27b.
Similarly, when I < 0, vD = I R2 = I 10000 as shown in Fig

voltage VA, where VA > 0. b) Find the incremental change in the current
ia for an incremental change in the voltage va at the operating point VA,
IA. c) By what fraction does ia change for a y percent change in va? d)
Suppose the nonlinear device is biase

AiB iCi + AiBiCi + AiBiCi. (5.46) Figure 5.30 shows a gate-level full
adder circuit based on the logic expressions for Si and Ci+1. We can
create a two bit adder out of a pair of one-bit full adders by feeding the
carry-out bit (Ci+1) of one adder to the

element laws for this circuit are v0 = 2 V v1 = 3i1 v2 = 2i2 i3 = 3 A.
Applying KCL to the two upper nodes gives us i0 + i1 + i2 = 0 i1 = i3.
Applying KVL to the two internal loops yields v0 = v2 v2 = v3 + v1.
Solving the preceding eight equations, we get

the sum of the appropriate mutual conductances elsewhere. Further,
the solution of such a set of linear simultaneous equations will always
result in an expression of the general form of Equation 3.102, in which
the voltage or current we are trying to eval

used to implement logic procedures. For example, consider the logical
if statement: If X is TRUE AND Y is TRUE then Z is TRUE else Z is
FALSE. We can represent this statement using a boolean equation as: Z
= X AND Y. In the previous equation, Z is true on

source with voltage V, the voltage across R2 is given by R2/(R1 + R2)
V. Current divider relation means that when two resistors with values
R1 and R2 are connected in parallel across a current source with current
I, the current through R2 is given by R1/(

number 110 represents 2, and the number 010 represents 2. When the
interpretation of the leading bit (sign bit or value bit) is not clear from
the context, to avoid confusion, it is important to indicate the numbering
system being assumed when specifying

1.5 V (4.5 V 3 V), which is the difference between VOH, the
minimum legal output voltage for a logic 1, and VIH, the minimum
input voltage recognized by a receiver as a logic 1. Valid 1 Valid 0 0 V 5
V Sender Receiver 1 0 0 1 VIH VIL Forbidden region VOH

+ vi = 11 V. N1 N2 i 1 i 2 + i S - v v (V) 1 -1 -1 1 i 1(A) v (V) 1 -1 1 i
2(A) 2 FIGURE 4.55 v) Now, find the exact value of the ia using ia = iA
IA. vi) What is the error in the value of ia computed using the small
signal method? problem 4.2 The circui

that Yehaas adders satisfy Discos static discipline and so they can be
used as replacements for Discos existing adders. 254 CHAPTER FIVE
the digital abstraction example 5.2 violating a static discipline Yikes
discovers that Disco is considering switching

incremental analysis on the circuit by following these two steps: 1. Find
the DC operating variables ID and VO by setting all small-signal sources
to zero. This will require a nonlinear analysis using one of the nonlinear
approaches 226 CHAPTER FOUR analy

11 discusses energy and power issues in digital systems and introduces
CMOS logic. Chapter 12 analyzes second order transients in networks. It
also discusses the resonance properties of RLC circuits from a timedomain point of view. Chapter 13 discusses si

PROBLEMS the digital abstraction 5 Value discretization forms the
basis of the digital abstraction. The idea is to lump signal values that fall
within some interval into a single value. We saw an example of value
discretization earlier in Figure 1.45 (rep

+ Y) shown in Table 5.4. The two expressions are in fact equivalent.
This should be self-evident since both expressions represent the same
truth table, but this fact will become obvious after Section 5.5 (and
specifically, Example 5.13) shows how such log

of gates used. i) Repeat part (d) and attempt to minimize the number of
gates used, assuming that the inputs are available both in their true and
complement forms. In other words, assume that in addition to W, X, and
Y, the inputs W, X, and Y, are also av

Equation 2.48 will become a primitive in our circuit vocabulary. It is
helpful to build up a set of such primitives, which are really solved
simple cases, to speed up circuit analysis, and to facilitate intuition. A
simple mnemonic: For the voltage v2, ta

network. Examination of either the two equations, Equations 3.121 and
3.115, or the two figures, Figures 3.56 and 3.76 show that there is a
simple relation between voc and isc. Working from the figures, we can
calculate the open-circuit voltage of each ci

voltage of 5 V is an element property, while v is a terminal variable that
we have defined. Similarly, the polarity markings inside the circle are a
property of the source, while the polarity markings outside the circle
representing the source relate to t

zero, that is, if R3 R1 + R3 = R4 R2 + R4 (3.130) or equivalently R3 R1
= R4 R2 . (3.131) Thus if R5 is replaced by a voltmeter, the circuit can
be used to find an unknown resistor, say R3, in terms of three known
resistors. Make one of the resistors, say

first looks at the output voltage levels required by Discos static
discipline. They observe that the 4.5-V output produced by their new
adders falls within Discos legitimate range for a logical 1 (between
VOH = 4 V and 5 V), thus satisfying the VOH requir

bit signals are commonly transmitted by allocating multiple wires one
for each bit, or occasionally, by time multiplexing multiple bits on a
single wire. This approach of representing numbers in the binary system
is discussed further in Section 5.6. For n