voltage of 5 V is an element property, while v is a terminal variable that
we have defined. Similarly, the polarity markings inside the circle are a
property of the source, while the polarity markings outside the circle
representing the source relate to t
zero, that is, if R3 R1 + R3 = R4 R2 + R4 (3.130) or equivalently R3 R1
= R4 R2 . (3.131) Thus if R5 is replaced by a voltmeter, the circuit can
be used to find an unknown resistor, say R3, in terms of three known
resistors. Make one of the resistors, say
first looks at the output voltage levels required by Discos static
discipline. They observe that the 4.5-V output produced by their new
adders falls within Discos legitimate range for a logical 1 (between
VOH = 4 V and 5 V), thus satisfying the VOH requir
bit signals are commonly transmitted by allocating multiple wires one
for each bit, or occasionally, by time multiplexing multiple bits on a
single wire. This approach of representing numbers in the binary system
is discussed further in Section 5.6. For n
current I through the current source. KCL for Node 2 in terms of node
voltages and element values is given by: 3 V 7 V 4 k + 3 V 7 V 1 k +
3 V 8 V 1 k + I = 0. Simplifying, we obtain I = 10 mA. In summary, a
voltage is always defined as the potential diff
1? To eliminate such confusion, we further prescribe a forbidden region
that separates the two valid regions. We further allow the behavior of the
receiving device to be undefined if it sees a voltage in the forbidden
region. Thus, the correspondence betw
network. Examination of either the two equations, Equations 3.121 and
3.115, or the two figures, Figures 3.56 and 3.76 show that there is a
simple relation between voc and isc. Working from the figures, we can
calculate the open-circuit voltage of each ci
Equation 2.48 will become a primitive in our circuit vocabulary. It is
helpful to build up a set of such primitives, which are really solved
simple cases, to speed up circuit analysis, and to facilitate intuition. A
simple mnemonic: For the voltage v2, ta
of gates used. i) Repeat part (d) and attempt to minimize the number of
gates used, assuming that the inputs are available both in their true and
complement forms. In other words, assume that in addition to W, X, and
Y, the inputs W, X, and Y, are also av
+ Y) shown in Table 5.4. The two expressions are in fact equivalent.
This should be self-evident since both expressions represent the same
truth table, but this fact will become obvious after Section 5.5 (and
specifically, Example 5.13) shows how such log
and the diode current will vary only by a small amount around ID (as
depicted in the graphical sketch in Figure 4.37) due to the small signal vI
superimposed on the DC input voltage. Thus a sensible approach is to
model the diode characteristic accurately
Consider the transmission of data A C B (a) Z Stuck at 1 A C B (b) Z
Stuck at 1 A C B (c) Z Stuck at 1 Stuck at 1 A C B (d) Z Stuck at 0 Stuck
at 0 FIGURE 5.45 over a noisy wire that picks up a maximum of 80 mV
symmetric peak-to-peak noise per centimeter.
demultiplexer module is shown in Figure 5.37. The demultiplexer has
two select signals, S1 and S0. The select signals determine on which of
the outputs (OUT0, OUT1, OUT2, or OUT3) the input IN appears. As
illustrated in the figure, IN appears at output OU
Figure 2.1 at which three branches meet. Similarly, b is a node at which
two branches meet. ab and bc are examples of branches in the circuit.
The circuit has five branches and four nodes. Since we assume that the
interconnections between the elements in
the voltage thresholds: VIL = 0.8 V, VOL = 0.3 V, VIH = 3.0 V, and
VOH = 4.5 V. Will a YTL inverter driving the input of E B C A F D 0
VIL VIH 5 V VOL VOH 5 V VIN VOUT FIGURE 5.42 C1 Adder C0
A0 A1 B1 B0 S1 S0 FIGURE 5.44 5.7 Summary CHAPTER FIVE 281
an N
deflection will be proportional to vR, and hence to iD, assuming resistor
R obeys Ohms law, and the horizontal and vertical amplifier inputs to
the oscilloscope draw negligible current. 1.6.3 THE CURRENT
SOURCEANOTHER IDEAL TWO-TERMINAL ELEMENT In some
fi
physical structure in Section 6.7. 6.3 The MOSFET Device and Its S
Model CHAPTER SIX 289 F IGUR E 6.7 Discrete MOSFETs. The
rightmost device with three leads contains a single MOSFET, while the
middle package contains multiple MOSFETs. (Photograph Courtes
solve the problem by linear circuit methods. Note from Equation 4.62
that the first term in Equation 4.61, the DC current ID, is independent of
vD. It depends only on the circuit parameters and the DC voltage VD
which is the same as the DC source voltage
bulb current if the bulb and 2- resistor are connected in series to the
battery. problem 4.4 a) Assuming the diode can be modeled as an ideal
diode, and R1 = R2, plot the waveform vo(t) for the circuit in Figure
4.57, assuming a triangle wave input. Write
Thvenin equivalent for the circuit in Figure 3.112 at the terminals AA .
180 CHAPTER THREE network theorems 12 V 6 3 1 A A + - A
FIGURE 3.112 e x e r c i s e 3.12 In the network in Figure 3.113, find an
expression for v2. R1 v3 I3 - + R2 v + 2 - FIGURE 3.
equivalent, the Norton 3.6 Thvenins Theorem and Nortons Theorem
CHAPTER THREE 169 equivalent circuit can also be used to model the
effect of the given network on other circuits external to the network. A
Method for Determining the Norton Equivalent Circui
3.3 THE NODE METHOD Perhaps the most powerful approach of
circuit analysis is referred to as node analysis. Node analysis is based on
the combination of element laws, KCL, and 126 CHAPTER THREE
network theorems KVL, just as was the basic approach presente
to the left of the source is, from Equations 2.94 and 2.58, G = (G1 +
G2)G3 G1 + G2 + G3 . (3.105) Hence, from the current divider relation,
the current through R3 is iR3 = GI G + G4 . (3.106) Now e1C can be
found from the relation e1C = iR3 G1 + G2 (3.10
PROBLEMS the digital abstraction 5 Value discretization forms the
basis of the digital abstraction. The idea is to lump signal values that fall
within some interval into a single value. We saw an example of value
discretization earlier in Figure 1.45 (rep
11 discusses energy and power issues in digital systems and introduces
CMOS logic. Chapter 12 analyzes second order transients in networks. It
also discusses the resonance properties of RLC circuits from a timedomain point of view. Chapter 13 discusses si
applying some form of excitation to the device terminals and obtaining
the relationship between the values of i and v. One of the simplest inputs
we can apply is a current source providing a current itest, as illustrated
in Figure 2.61b. The figure also s
1. Its outputs are a function of its inputs alone. 2. It satisfies the static
discipline. Figure 5.14 shows several useful gate symbols. We have
already seen the gate-level representation of the AND function. The OR
gate performs the OR function of its in
input voltage at G impacts the behavior of the MOSFET at its D and S
terminals, the voltages or currents at its D and S terminals have no
impact on G. 2. Second, the infinite resistance seen at the gate (G
terminal) of a MOSFET makes it have no effect on
incremental resistance rd = 25 . Similarly, for ID = 1.45 A, rd = 0.017 .
Note: The incremental resistance in general is not the same as the
resistor Rd used in the piecewise linear model of WWW Figure 4.33c.
There we were trying for a fit over a large ra