K-Maps Difficult in Visualization for
six variables and above
Not software adaptable
1. Find all the prime implicants
f ( a , b, c , d )
group 0
0 0000
group 1
1 0001
2 0010
8 1000
group 2
5
6
9
10
group 3
7 0111
14 1110
0101
0110
1001
1010
m(0,1,2,5,6,7,
ADVANTAGES OF DIGITAL SYSTEMS
- Reproducibility of results
- Ease of design
- Programmability
- Speed
- Cost
- Integrated Circuits
- COMBINATIONAL
(Outputs depend only on present inputs)
-SEQUENTIAL
( Depends on present & Previous inputs)
Involve timing a
Multiplication
Some general observations
1. Multiplication involves the generation of
partial products one for each digit in the
multiplier.
2. Partial products are summed to produce
the final product.
3. Partial products are very simple to define
for bin
Latches are transparent (=> any change
on the inputs is seen at the outputs
immediately).
This causes synchronization problems!
Solution: use latches to create flip-flops that
can respond (update) ONLY on SPECIFIC
times (instead of ANY time).
D FLIP-FLOP
A De-multiplexer is a logic circuit that transmit
Information on a single line on one of 2n output
lines
Selection of output line depends on the value of
n select lines
A Decoder with enable input can function
as a De-multiplexer
Back to HDL
.
2-to-4 Line D ecoder
B/
A/
/Gate - level description of a 2-to-4 line decoder
module decoder_g1 ( A,B,E,D);
input A, B, E;
output [0:3]D;
wire Anot, Bnot, Enot;
not
B/
n1(Anot, A),
n2(Bnot, B),
n3( Enot, E);
A/
nand
n4 (D[0], Anot, Bnot, Eno
DESIGN WITH UNUSED STATES
Design the circuit using D Flip Flops
Answer:
Da=A B x
Db = C x + A+ B C x
Dc=A B x +Cx +Ax
Y= A x
The circuit is self correcting
STATE REDUCTION
STATE TABLE
Present
state
a
b
c
d
e
f
g
Next State
X=0
a
c
a
e
a
g
a
X=1
b
d
d
f
f
Von Neumann architecture
Single bank of memory which processor
accesses through a single set of address
and data lines.
Processor core
Address bus
Data bus
Memory
Harvard Architecture
The Processor is connected to two
independent memory banks via two
inde
EECE 256 - Sections 101, 102 &103 - midterm
THE UNIVERSITY OF BRITISH COLUMBIA
Department of Electrical & Computer Engineering October 27, 2005 EECE 256 Sections 101, 102 & 103 Student name:_ S#: _
Midterm 50 minutes
Closed book No calculators are allowed
EECE - Sections 101 &102 - midterm
THE UNIVERSITY OF BRITISH COLUMBIA
Department of Electrical & Computer Engineering October 26, 2006 EECE 256 Sections 101 & 102 Student name:_ S#: _
Midterm 50 minutes
Closed book No calculators are allowed
1.
Design a 4
EECE - Sections 101&102 - midterm
THE UNIVERSITY OF BRITISH COLUMBIA
Department of Electrical & Computer Engineering
Dr. Panos Nasiopoulos
November 5, 2007
EECE 256 Sections 101 & 102 Student name:_ S#: _Section:_
Midterm 50 minutes
Closed book No calcula
1.
[30 points] Short Questions 1.a. Prove or disprove that the operators (,XOR) form a complete set. Remember that the operator () is implication such that:
A B AB 0 0 1 1 0 1 0 1 1 1 0 1
1.b. Realize a 5-input NOR function using 2-input NOR gates only. 1
BITS Pilani
Pilani Campus
BITS Pilani
Hardware Software Codesign
Ashish Mishra
[email protected]
BITS Pilani
Pilani Campus
Lecture-10
Time Profiling
Introduction to profiler
It is a useful tool for measuring the performance of a progr
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Y
0
1
1
0
1
0
0
1
3-input EX-OR
Y=A B C
= A B C+A BC
AB C +ABC
= (1,2,4,7)
- ODD Function
1
1
1
1
1
1
1
1
Odd Function
F=A B C
Even Function
F = (A B C)
1
1
1
1
1
F=A B C D
- ODD FUNCTION
1
1
1
1
1
1
1
Ripple Counter
Ripple
Synchr onous Bi nar y Count er s
Design with D Flip- Flops
Design with J- K Flip- Flops
Serial Vs. Parallel Counters
Up- down Binary Counter
Bi nar y Count er wi t h Par al l el Load
BCD Count er , A r b i t r ar y sequence Count er