EECE 488 Analog CMOS Integrated Circuit Design
Design Project: Opamp Design
Due: Monday December 16th, 2013, by 11:59pm
Design and simulate (using HSPICE) a two-stage operational amplifier based on the following topology
in the 0.35-m CMOS process that we
EECE 488 Analog CMOS Integrated Circuit Design
Design Project: Opamp Design
Due: Saturday April 20, 2013 at 23:59
The objective of this project is to design a differential input single-ended output CMOS opamp for a
specific application where the opamp wil
hspice.book : hspice.ch07
1 Thu Jul 23 19:10:43 1998
Chapter 7
Performing Transient Analysis
Star-Hspice transient analysis computes the circuit solution as a function of time
over a time range specified in the .TRAN statement.
This chapter covers the fol
R$<gl~iong~l Pro 10le
5.19. The circuit shown in Fig. 5.43 exhibits a negative input capacitance. Calculate the input
impedance of the circuit and identify the capacitive component.
V00
+
Y 0_ C,
M1 _
(b)
Figure5.43
6.6. Neglecting other capacitances. c
page 5 cf 5
6.11. Consider the cascode stage shown in Fig. 6.41. In our analysis of the frequency response of
a cascode stage, we assumed that the gate-drain overlap capacitance of M1 is multiplied by
gm; /(gm2 + gmbz). Recall from Chapter 3, however, tha
Paj 2. cl: 5
6.9. Calculate the gain of each circuit in Fig. 6.39 at very low and very high frequencies. Neglect all
other capacitances and assume A = 0 for circuits (a) and (b) and y = 0 for all of the circuits.
Von
Vb2| M3
Figure 6.39
6.10. Calculate
THE UNIVERSITY OF BRITISH COLUMBIA
Department of Electrical and Computer Engineering
ANALOG CMOS IC DESIGN
DESIGN PROJECT:
OP-AMP DESIGN
prepared by
Ali Rafie Ravndi 31751100
In collaboration with
Navid Fattahi
Shahin Bayat
Alireza Afshar
In Partial Fulfi
1. Find the maximum bias current I for which the transistor in the following circuit
operates in the saturation region. [10 marks]
Assume it = y: 0, VTH = 0.5 v, uncm = 1 111255ng, (W/L)NMGS = 10, RD = 109.
it
RD=1
Write your answer in this box 2. The
THE UNIVERSITY OF BRITISH COLUMBIA
Department of Electrical and Computer Engineering
EECE 488 Analog CMOS Integrated Circuit Design
Midterm Exam
Due: Thursday, October 24, 2013 at 8:00 am
Time: 80 minutes
This is an open book exam and calculators are allo
EECE488 Analog CMOS Integrated Circuit Design
Assignment 1
Due: Tuesday October 8th, 2013 at 9:30am
1. The transit frequency, fT, of a MOS transistor is defined as the frequency at which the
small-signal current gain of the device drops to unity while the
EECE488 Analog CMOS Integrated Circuit Design
Assignment 2
Due: Tuesday October 15th, 2013 at 8:00 am
1. Consider the following circuit:
V DD
V out(t)
M1
V in(t)
M2
V bias
The technology parameters are:
(NMOS)=(PMOS)=0 V-1, =0, VDD=3.0 V, VTH(NMOS)=|VTH(P
EECE488 Analog CMOS Integrated Circuit Design
Assignment 4
Due: Tuesday November 26th, 2013 at 8:00am
1. Consider the following circuit. (This circuit is sometimes referred to as a self-biased
current source).
VDD
R
M1
Iout
M2
M3
M0
GND
M4
GND
GND
Assume