P6.1. The on-resistance of a unit-sized NMOS device.
LINEAR | SATURATION
On-resistance of a unit-sized NMOS device
0 0.2 0.4 0.6 0.8 'l 1.2
The average on-resistance is approximately 151d}. The expression for the average
P5.1. For each probiem, restate each Boolean equation into a form such that it can be translated
into the p and n-complex of a CMOS gate.
P2. 1. a) The solution for the NMOS case is based on Example 2.4:
The equation for Vm is: VTU = VFB — 205E — Q3
Calculate each individual component.
(gig = E In ”* = —0.026lnL0m = —0.44 V
q NA 1.4x 10
$50 = ¢Fp _ ¢G(gate} = ‘0-44— 0
P4. 1. Problem should refer to Figure P42.
a. All inverters but the CMOS inverter consume static power then the output is high.
Notice that in the first three inverters when the input is high, there is always a direct
connection from VDD to GND.
The general approach for the first two parameters is to ﬁgure out which variables should
remain constant, so that when you have two currents, you can divide them, and every
variable but the ones you want to calculate remain. In this case,
P11. Assume that all nodes start at (N. The ﬁrst row outputs will be at Van —VT. Since these
nodes are also the gate nodes of the second row of transistors, their source nodes will be
at ‘VDD —2VT . Likewise, the last row of transistors have vol
P1.1. To express each equation as surnwof—product and as a product—of—surn first write the truth
table then create a Kamaugh map from the truth table. Then use the 1’s for sum-of
products and 0’s for product of sums.
a. F = C321 + C§A+ EBA+ CBA