We often want to do numerical computations in digital systems so we need to
understand how to represent and manipulate binary numbers (and, in general, in
number systems other than decimal).
ECE124 Digital Circuits and Systems
Impact of flip-flop type on sequential circuit design
Flip-flops hold the current state information and the next state information is
determined by the flip-flop input equations.
When designing a synchronous circuit, using DFF is an obvious choice because
VHDL process statements
Recall that concurrent signal assignment statements all operate in parallel.
The VHDL process statement is effectively a block around a bunch of logic and
Inside of a process statement, statements are executed sequentiall
Algorithmic state machines (ASM)
An alternative to a state diagram which is sometimes nicer when our hardware is
implementing an algorithm that can be drawn as a flowchart.
The ASM is tied closely with a hardware implementation.
The ASM consists of three
Synchronous circuit analysis
Given a circuit (containing combinational logic and flip-flops), synchronous circuit
analysis involves figuring out what the circuit is doing.
i.e., How does the circuit transition from state to state as clock edges arrive?
State minimization in asynchronous circuits
Similar to the minimization we did with synchronous sequential circuits.
Lots of opportunity for state minimization in asynchronous flow tables:
Lots of dont care outputs for unstable states (since we wont stay
Asynchronous Sequential Circuits
A type of circuit without clocks (therefore NO flip-flops), but with the concept of
The concept of memory is obtained through the use of: latches and/or circuit
delay and combinational loops.
A hazard is a momentary unwanted switching transient at a logic functions output
(i.e., a glitch).
Hazards/glitches occur due to unequal propagation delays along different paths in a
Can take steps to try and eliminate hazar
Read Only Memory (ROM)
Device that allows permanent storage of information.
Device has k input (address) lines and n output (data) lines.
We can store 2k x n bits of information inside the device.
The address lines specify a memory location and the data o
Programmable Logic Devices
Many different programmable logic devices available; e.g., PLA, PAL, CPLD, FPGA, etc
The idea is that these devices are generic in that they can be programmed to
implement a wide variety of different types of digital circuit.
A single FF stores one bit A group of n FFs
stores n-bits and is called an n-bit register.
When clear=0, all flip-flop outputs are forced
to zero (active low reset).
When clear=1, the rising edge of the clock
(the active clock e
Circuits with simple logic gates are known as combinational circuits. These are the
types of circuits we have talked about up to this point in the course.
We can include storage elements into a circuit that act like memory and store a
Factoring (and multi-level implementations)
Sometimes 2-level implementations can just be large; i.e., even with simplification,
we still end up with large gates and many of them.
Sometimes, the solution is to factor an equation to see if there are simple
Digital circuits and systems are essentially a means to perform computation
and logical operations via machines.
It turns out that machines to perform computation and logic operations deal
best when working with only binary values; i.e., on
Logic Minimization with Karnaugh Maps (KMaps)
Boolean algebra can be used to find minimal SOP (POS) logic equations, but it
is hard to automate and not very systematic.
For small logic functions (<=5 inputs), we can use Karnaugh Map (KMap).
Combinatorial circuits (arithmetic)
Some combinational circuits are very comment and it is worth looking at
them in more detail.
One particular class of very useful circuits are arithmetic circuits; i.e., those
circuits used for performing operations su
Combinational circuits (other useful combinational blocks)
Many types of useful combinational circuits such as comparators, encoders
and decoders, multiplexers and demultiplexers, and so on.
We should be familiar with such blocks since they occur so often
Often we will have a VHDL Description of part of a circuit that we would like to use inside of
As an example, consider building an n-bit ripple adder from 1-bit full adders.
We can use VHDL descriptions inside of
Other types of concurrent VHDL signal assignments
The <= operator is not the only means by which we can perform combinational
assignments in VHDL.
There are other concurrent signal assignment operators that make writing VHDL a bit
ECE124 Digital C
What Is VHDL (IEEE Standard 1076)?
VHDL is an acronym that stands for VHSIC Hardware Description Language.
The acronym VHSIC in turn stands for Very-High Speed Integrated Circuit program.
Program sponsored by US Department of Defense (DOD) with the goal o
Clocked (synchronous) sequential circuits
Synchronous sequential circuits have the concept of memory and use a clock to
determine when things happen in a circuit.
Chip level timing
Have discussed some issues related to timing analysis.
Talked briefly about longest combinational path for a combinational circuit.
Talked briefly about timing with flip-flops; i.e.,
Data input must be stable before active clock edge (s
Implementing logic gates in CMOS
Logic gates are implemented via transistors.
One popular technology for implementing transistors is Complementary Metal Oxide
Semiconductor (CMOS) technology.
Transistors effectively implement switches. There are two ty
Minterms and Maxterms
Every n variable truth table has 2n rows. For each row, we can write its minterm (an AND
which evaluates to 1 when the associated input appears, otherwise 0) and maxterm (an OR
which evaulates to 0 when the associated input appears,
A dierent graphical representation of a logic function equivalent to a truth table (ie. holds
the same value). Its not tabular, but more like a matrix. Note that it only works for up to
It is useful becau
Digital Circuits Exam Notes
Wednesday, April 17, 2013
o Time PRIOR to active clock edge where inputs MUST be stable
o Time AFTER active clock edge where inputs MUST be stable
o Time afte