Introduction
Digital circuits and systems are essentially a means to perform computation
and logical operations via machines.
It turns out that machines to perform computation and logic operations d
Algorithmic state machines (ASM)
An alternative to a state diagram which is sometimes nicer when our hardware is
implementing an algorithm that can be drawn as a flowchart.
The ASM is tied closely wit
Synchronous circuit analysis
Given a circuit (containing combinational logic and flip-flops), synchronous circuit
analysis involves figuring out what the circuit is doing.
i.e., How does the circuit
State assignment
Given a state table or state diagram with symbolic states, we need to assign binary
patterns to the states.
Since both circuit outputs and flip-flop input equations depend on current
State minimization in asynchronous circuits
Similar to the minimization we did with synchronous sequential circuits.
Lots of opportunity for state minimization in asynchronous flow tables:
Lots of do
Race Conditions; Critical and Non-Critical Races
A race condition occurs in an asynchronous circuit when 2 or more state variables
change in response to a change in the value of a circuit input.
Unequ
Asynchronous Sequential Circuits
A type of circuit without clocks (therefore NO flip-flops), but with the concept of
memory.
The concept of memory is obtained through the use of: latches and/or circu
Hazards
A hazard is a momentary unwanted switching transient at a logic functions output
(i.e., a glitch).
Hazards/glitches occur due to unequal propagation delays along different paths in a
combinati
Read Only Memory (ROM)
Device that allows permanent storage of information.
Device has k input (address) lines and n output (data) lines.
We can store 2k x n bits of information inside the device.
The
Programmable Logic Devices
Many different programmable logic devices available; e.g., PLA, PAL, CPLD, FPGA, etc
The idea is that these devices are generic in that they can be programmed to
implement
VHDL process statements
Recall that concurrent signal assignment statements all operate in parallel.
The VHDL process statement is effectively a block around a bunch of logic and
control.
Inside of a
Impact of flip-flop type on sequential circuit design
Flip-flops hold the current state information and the next state information is
determined by the flip-flop input equations.
When designing a sync
Logic Minimization with Karnaugh Maps (KMaps)
Boolean algebra can be used to find minimal SOP (POS) logic equations, but it
is hard to automate and not very systematic.
For small logic functions (<=
Combinatorial circuits (arithmetic)
Some combinational circuits are very comment and it is worth looking at
them in more detail.
One particular class of very useful circuits are arithmetic circuits;
Combinational circuits (other useful combinational blocks)
Many types of useful combinational circuits such as comparators, encoders
and decoders, multiplexers and demultiplexers, and so on.
We should
Component instantiations
Often we will have a VHDL Description of part of a circuit that we would like to use inside of
another circuit.
As an example, consider building an n-bit ripple adder from 1-
Other types of concurrent VHDL signal assignments
The <= operator is not the only means by which we can perform combinational
assignments in VHDL.
There are other concurrent signal assignment operator
What Is VHDL (IEEE Standard 1076)?
VHDL is an acronym that stands for VHSIC Hardware Description Language.
The acronym VHSIC in turn stands for Very-High Speed Integrated Circuit program.
Program spon
Clocked (synchronous) sequential circuits
Synchronous sequential circuits have the concept of memory and use a clock to
determine when things happen in a circuit.
inputs
combinatorial
circuit
outputs
Sequential circuits
Circuits with simple logic gates are known as combinational circuits. These are the
types of circuits we have talked about up to this point in the course.
We can include storage el
Registers
A single FF stores one bit A group of n FFs
stores n-bits and is called an n-bit register.
Illustration:
When clear=0, all flip-flop outputs are forced
to zero (active low reset).
When cl
Chip level timing
Have discussed some issues related to timing analysis.
Talked briefly about longest combinational path for a combinational circuit.
Talked briefly about timing with flip-flops; i.e.,
Implementing logic gates in CMOS
Logic gates are implemented via transistors.
One popular technology for implementing transistors is Complementary Metal Oxide
Semiconductor (CMOS) technology.
Trans
ECE 124 Digital Circuits and Systems
So minterms and maxterms are created opposite of each other.
Page 27
For each row of the truth table, create an OR of the literals according to
the fllowing rule
NOR
Performs the OR then NOT function. It looks like an OR gates with a NOT circle immediately after. f = ab + b!c = b(a + !c)
Table 6: NOR,
x y
0 0
0 1
1 0
1 1
f =x+y
f
1
0
0
0
Note that NAND and NOR
Minterms and Maxterms
Every n variable truth table has 2n rows. For each row, we can write its minterm (an AND
which evaluates to 1 when the associated input appears, otherwise 0) and maxterm (an OR
w
Table 9:
x
0
1
Buer
f
0
1
Karnough Maps
A dierent graphical representation of a logic function equivalent to a truth table (ie. holds
the same value). Its not tabular, but more like a matrix. Note tha