University of Waterloo
Faculty of Engineering
Department of Electrical and Computer Engineering
ECE 124, Digital Circuits and Systems
Winter 2016
J.G. Thistle, EIT 3113, ext. 32910,
jthistle@kingcong.uwaterloo.ca
Calendar description
Number systems and Bo
ECE 124 Digital Circuits and Systems
Consider two functions and how we can implement them with gates.
Page 22
The implementation of a circuit is known as synthesis and we can draw circuits
implementing functions using the logic gate symbols.
While Bool
Department of Electrical and Computer Engineering
ECE 124: Digital Circuits and Systems
Winter Term 2013
COURSE INSTRUCTORS:
Name
Andrew Kennings
Class
LEC001/LEC002
Office
EIT 4102
Ext
36909
Email
akenning@ece.uwaterloo.ca
LAB INSTRUCTORS:
Name
Allaa Hil
Implementing logic gates in CMOS
Logic gates are implemented via transistors.
One popular technology for implementing transistors is Complementary Metal Oxide
Semiconductor (CMOS) technology.
Transistors effectively implement switches. There are two ty
Chip level timing
Have discussed some issues related to timing analysis.
Talked briefly about longest combinational path for a combinational circuit.
Talked briefly about timing with flip-flops; i.e.,
Data input must be stable before active clock edge (s
Programmable Logic Devices
Many different programmable logic devices available; e.g., PLA, PAL, CPLD, FPGA, etc
The idea is that these devices are generic in that they can be programmed to
implement a wide variety of different types of digital circuit.
Read Only Memory (ROM)
Device that allows permanent storage of information.
Device has k input (address) lines and n output (data) lines.
We can store 2k x n bits of information inside the device.
The address lines specify a memory location and the data o
Hazards
A hazard is a momentary unwanted switching transient at a logic functions output
(i.e., a glitch).
Hazards/glitches occur due to unequal propagation delays along different paths in a
combinational circuit.
Can take steps to try and eliminate hazar
Asynchronous Sequential Circuits
A type of circuit without clocks (therefore NO flip-flops), but with the concept of
memory.
The concept of memory is obtained through the use of: latches and/or circuit
delay and combinational loops.
Asynchronous sequenti
State minimization in asynchronous circuits
Similar to the minimization we did with synchronous sequential circuits.
Lots of opportunity for state minimization in asynchronous flow tables:
Lots of dont care outputs for unstable states (since we wont stay
Synchronous circuit analysis
Given a circuit (containing combinational logic and flip-flops), synchronous circuit
analysis involves figuring out what the circuit is doing.
i.e., How does the circuit transition from state to state as clock edges arrive?
W
Algorithmic state machines (ASM)
An alternative to a state diagram which is sometimes nicer when our hardware is
implementing an algorithm that can be drawn as a flowchart.
The ASM is tied closely with a hardware implementation.
The ASM consists of three
VHDL process statements
Recall that concurrent signal assignment statements all operate in parallel.
The VHDL process statement is effectively a block around a bunch of logic and
control.
Inside of a process statement, statements are executed sequentiall
Impact of flip-flop type on sequential circuit design
Flip-flops hold the current state information and the next state information is
determined by the flip-flop input equations.
When designing a synchronous circuit, using DFF is an obvious choice because
Registers
A single FF stores one bit A group of n FFs
stores n-bits and is called an n-bit register.
Illustration:
When clear=0, all flip-flop outputs are forced
to zero (active low reset).
When clear=1, the rising edge of the clock
(the active clock e
Sequential circuits
Circuits with simple logic gates are known as combinational circuits. These are the
types of circuits we have talked about up to this point in the course.
We can include storage elements into a circuit that act like memory and store a
Clocked (synchronous) sequential circuits
Synchronous sequential circuits have the concept of memory and use a clock to
determine when things happen in a circuit.
inputs
combinatorial
circuit
outputs
next state
function flip-flops
current
state
clock
Whe
ECE 124 Digital Circuits and Systems
AND (2-inputs)
OPERATOR
SYMBOL
TRUTH TABLE
Page 10
The logic operators AND, OR, NOT are implemented via logic gates
(which, in turn, are implemented with transistors).
We have symbols to represent the different logic f
Binary logic and Boolean algebra; truth tables; logic gates.
Minterms, maxterms and 2-level logic implementations
Sum-of-products
Product-of-sums
NAND/NOR only circuits.
Logic minimization using Karnaugh Maps.
Clearly, knowledge of this material is
Digital Circuits Exam Notes
Wednesday, April 17, 2013
Flip Flops
Timing Diagrams
Setup time
o Time PRIOR to active clock edge where inputs MUST be stable
Hold time
o Time AFTER active clock edge where inputs MUST be stable
Clock-to-output time
o Time afte
Table 9:
x
0
1
Buer
f
0
1
Karnough Maps
A dierent graphical representation of a logic function equivalent to a truth table (ie. holds
the same value). Its not tabular, but more like a matrix. Note that it only works for up to
ve inputs.
It is useful becau
Minterms and Maxterms
Every n variable truth table has 2n rows. For each row, we can write its minterm (an AND
which evaluates to 1 when the associated input appears, otherwise 0) and maxterm (an OR
which evaulates to 0 when the associated input appears,
NOR
Performs the OR then NOT function. It looks like an OR gates with a NOT circle immediately after. f = ab + b!c = b(a + !c)
Table 6: NOR,
x y
0 0
0 1
1 0
1 1
f =x+y
f
1
0
0
0
Note that NAND and NOR gates are universal (they can implement any function).
ECE 124 Digital Circuits and Systems
So minterms and maxterms are created opposite of each other.
Page 27
For each row of the truth table, create an OR of the literals according to
the fllowing rule: If a variable x has value 0 in the row, include its +